I2S_CLK

MCLK

pll_input

I2S_INT_CLK

PLL

I2S_INPUT_CLK

I2S

Interface

Stereo DAC

125/128

I2S_OUTPUT_CLK

%2

1

0

0

1

fast_clock

DAC

Clock

Gen

%R

DSP CLK

0

1

audio_dk_sel

R Div input clock

PLL

output

clock

PLL input

clock

Clock Gen

input clock

LM4937

SNAS369J – OCTOBER 2006 – REVISED MAY 2013

www.ti.com

By default the stereo DAC operates at 250*fs, i.e. 12.000MHz (at the clock generator input clock) for 48kHz data.

It is expected that the PLL be used to drive the audio system unless a 12.000MHz master clock is supplied. The

PLL can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output of

the PLL.

Common Clock Settings for the DAC

The DAC can work in 4 modes, each with different oversampling rates, 125,128,64 & 32. In normal operation

125x oversampling provides for the simplest clocking solution as it will work from 12.000MHz (common in most

systems with Bluetooth or USB) at 48kHz exactly. The other modes are useful if data is being provided to the

DAC from an uncontrollable isochronous source (such as a CD player, DAB, or other external digital source)

rather than being decoded from memory. In this case the PLL can be used to derive a clock for the DAC from the

I2S clock.

The DAC oversampling rate can be changed to allow simpler clocking strategies, this is controlled in the DAC

SETUP register but the oversampling rates are as follows:

DAC MODE

Over sampling Ratio Used

00

125

01

128

10

64

11

32

The following table describes the clock required at the clock generator input for various clock sample rates in the

different DAC modes:

Fs (kHz)

DAC Oversampling Ratio

Required CLock at DAC Clock Generator

Input (MHz)

8

125

2

8

128

2.048

11.025

125

2.75625

11.025

128

2.8224

12

125

3

12

128

3.072

16

125

4

16

128

4.096

20

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