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SNJ54ALS109AJ Datasheet(PDF) 1 Page - Texas Instruments |
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SNJ54ALS109AJ Datasheet(HTML) 1 Page - Texas Instruments |
1 / 19 page SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL JK POSITIVEEDGETRIGGERED FLIPFLOPS WITH CLEAR AND PRESET SDAS198B − APRIL 1982 − REVISED AUGUST 1995 Copyright 1995, Texas Instruments Incorporated 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREQUENCY (MHz) TYPICAL POWER DISSIPATION PER FLIP-FLOP (mW) ′ALS109A 50 6 ′AS109A 129 29 description These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range of −55 °C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H LX X X L H L LX X X H† H† H H ↑ LL L H H H ↑ H L Toggle H H ↑ LH Q0 Q0 H H ↑ HH H L H H L X X Q0 Q0 † The output levels in this configuration are not specified to meet the minimum levels for VOH if the lows at PRE and CLR are near VIL maximum. Furthermore, this configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. SN54ALS109A, SN54AS109A...J PACKAGE SN74ALS109A, SN74AS109A...D OR N PACKAGE (TOP VIEW) SN54ALS109A, SN54AS109A...FK PACKAGE (TOP VIEW) NC − No internal connection 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1CLR 1J 1K 1CLK 1PRE 1Q 1Q GND VCC 2CLR 2J 2K 2CLK 2PRE 2Q 2Q 32 1 20 19 910 11 12 13 4 5 6 7 8 18 17 16 15 14 2J 2K NC 2CLK 2PRE 1K 1CLK NC 1PRE 1Q PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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