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SN74ACT3622-15PQG4 Datasheet(PDF) 7 Page - Texas Instruments |
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SN74ACT3622-15PQG4 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 31 page SN74ACT3622 256 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS247D – AUGUST 1993 – REVISED APRIL 1998 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 almost-empty flag and almost-full flag offset programming (continued) Table 1. Flag Programming FS1 FS0 RST1 RST2 X1 AND Y1 REGISTERS† X2 AND Y2 REGISTERS‡ H H ↑ X 64 X H H X ↑ X 64 H L ↑ X 16 X H L X ↑ X 16 L H ↑ X 8 X L H X ↑ X 8 L L ↑ ↑ Programmed from port A Programmed from port A † X1 register holds the offset for AEB; Y1 register holds the offset for AFA. ‡ X2 register holds the offset for AEA; Y2 register holds the offset for AFB. To load the FIFO AE flag and AF flag offset registers with one of the three preset values listed in Table 1, at least one of the flag-select inputs must be high during the low-to-high transition of its reset input. For example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be high when FIFO1 reset (RST1) returns high. Flag-offset registers associated with FIFO2 are loaded with one of the preset values in the same way with FIFO2 reset (RST2). When using one of the preset values for the flag offsets, the FIFOs can be reset simultaneously or at different times. To program the X1, X2, Y1, and Y2 registers from port A, both FIFOs should be reset simultaneously with FS0 and FS1 low during the low-to-high transition of the reset inputs. After this reset is complete, the first four writes to FIFO1 do not store data in RAM but load the offset registers in the order Y1, X1, Y2, X2. Each offset register uses port-A inputs (A7 – A0). The highest numbered input is used as the most-significant bit of the binary number in each case. Valid programming values for the registers range from 1 to 252. After all the offset registers are programmed from port A, the port-B input-ready (IRB) flag is set high and both FIFOs begin normal operation. FIFO write/read operation The state of the port-A data (A0 – A35) outputs is controlled by the port-A chip select (CSA) and the port-A write/read select (W/RA). The A0 – A35 outputs are in the high-impedance state when either CSA or W/RA is high. The A0 – A35 outputs are active when both CSA and W/RA are low. Data is loaded into FIFO1 from the A0 – A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low, and IRA is high. Data is read from FIFO2 to the A0 – A35 outputs by a low-to-high transition of CLKA when CSA is low, W/RA is low, ENA is high, MBA is low, and ORA is high (see Table 2). FIFO reads and writes on port A are independent of any concurrent port-B operation. Table 2. Port-A Enable Function Table CSA W/RA ENA MBA CLKA A0 – A35 OUTPUTS PORT FUNCTION H X X X X In high-impedance state None L H L X X In high-impedance state None L H H L ↑ In high-impedance state FIFO1 write L H H H ↑ In high-impedance state Mail1 write L L L L X Active, FIFO2 output register None L L H L ↑ Active, FIFO2 output register FIFO2 read L L L H X Active, mail2 register None L L H H ↑ Active, mail2 register Mail2 read (set MBF2 high) |
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