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SN74AHCT595DR Datasheet(PDF) 5 Page - Texas Instruments |
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SN74AHCT595DR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 25 page SN54AHCT595, SN74AHCT595 www.ti.com SCLS374N – MAY 1997 – REVISED JULY 2014 7.4 Thermal Information SN74AHCT595 THERMAL METRIC(1) D DB N NS PW UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 80.2 97.5 47.5 79.1 105.7 RθJC(top) Junction-to-case (top) thermal resistance 39.1 47.7 34.9 35.4 40.4 RθJB Junction-to-board thermal resistance 27.7 48.1 27.5 39.9 50.7 °C/W ψJT Junction-to-top characterization parameter 9.9 9.8 19.8 5.4 3.7 ψJB Junction-to-board characterization parameter 37.4 47.6 27.4 39.5 50.1 RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a n/a n/a (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) TA = 25°C SN54AHCT595(1) SN74AHCT595 PARAMETER TEST CONDITIONS VCC UNIT MIN TYP MAX MIN MAX MIN MAX IOH = –50 mA 4.4 4.5 4.4 4.4 VOH 4.5 V V IOH = –8 mA 3.94 3.8 3.8 IOL = 50 µA 0.1 0.1 0.1 VOL 4.5 V V IOL = 8 mA 0.36 0.44 0.44 0 to 5.5 II VI = 5.5 V or GND ±0.1 ±1(2) ±1 µA V IOZ VO = VCC or GND QA – QH 5.5 V ±0.25 ±2.5 ±2.5 µA ICC VI = VCC or GND IO = 0 5.5 V 4 40 40 µA One input at 3.4V, ΔICC (3) 5.5 V 2 2.2 2.2 mA Other inputs at VCC or GND Ci VI = VCC or GND 5 V 3 10 10 pF Co VO = VCC or GND 5 V 5.5 pF (1) Product Preview (2) On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. (3) This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC. 7.6 Timing Requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 3) TA = 25°C SN54AHCT595(1) SN74AHCT595 PARAMETER UNIT MIN MAX MIN MAX MIN MAX SRCLK high or low 5 5.5 5.5 tw Pulse duration RCLK high or low 5 5.5 5.5 ns SRCLR low 5 5 5 SER before SRCLK ↑ 3 3 3 SRCLK ↑ before RCLK↑(2) 5 5 5 tsu Setup time ns SRCLR low before RCLK ↑ 5 5 5 SRCLR high (inactive) before SRCLK ↑ 3.4 3.8 3.8 th Hold time SER after SRCLK ↑ 2 2 2 ns (1) Product Preview (2) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. Copyright © 1997–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: SN54AHCT595 SN74AHCT595 |
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