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DP84910VHG-50 Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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DP84910VHG-50 Datasheet(HTML) 2 Page - National Semiconductor (TI) |
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2 / 32 page  General Description (Continued) The pulse detector section detects the peaks of the analog pulses from the read preamplifier and converts them to digi- tal pulses whose leading edges represent the time position of the analog pulses’ peaks In order to not interpret noise on the baseline as input data hysteresis is included The hysteresis level for a data field is set at the SETHYSD pin while the hysteresis level for a servo field is set at the SETHYSS pin A third pin (SFIELD) is used to select be- tween these two levels of hysteresis This allows for the setting of different hysteresis levels for these two fields The data field hysteresis level is also selectable in 8 steps through bits in the control register (HYS VTH0 – HYS VTH2) with the level set at the SETHYSD pin as the nominal value The pulse detector section includes an automatic gain con- trol (AGC) circuit which normalizes the analog data signal to a constant amplitude The response of the AGC is partially controlled by one of the device’s pins (VAGCIN) Two VAGCIN pins (VAGCIND VAGCINS) are provided so that different capacitor values can be selected to provide differ- ent AGC time constants for data and servo field information The switching between these pinscapacitors is controlled by the SFIELD pin The SERVO control register bit can en- able (or disable) the SFIELD pin’s ability to control the amount of equalization provided to the on-chip channel fil- ter When enabled the state of the SFIELD pin selects be- tween two groups of control register bits (EQ0 EQ1 EQ2 and SERVO EQ0 SERVO EQ1 SERVO EQ2) which can separately determine the amount of equalization provid- ed This feature allows for an adjustment of the channel filter bandwidth in a servo field Thus the channel filter can have different bandwidths in a servo field and a data field The pulse detector section has a delayed low impedance switch at the gain controlled amplifier inputs (AMPIN1 AM- PIN2) which allows for rapid recovery from the write mode The amount of delay (either 17 msor3 4 ms) coming out of the low impedance mode is selectable through a bit in the control register (SLOW) A pattern insensitive fast respond- ing AGC circuit (with HOLD function) allows rapid head switch settling and embedded servo normalization Select- able delay (in four steps) in the qualification channel along with a ‘‘view internal signals’’ mode allow the timing and qualification channels to be optimally aligned Four gated servo detectors are incorporated for recovery of quadrature embedded servo information The four peak detected val- ues are available at the SERVO CAPACITOR outputs (SCAP1 – 4) Two servo difference amplifiers are provided Each difference amplifier output (DIFFAMP12) provides the difference between two of the servo peak detectors centered about an external reference voltage (VDIFF) The channel filter section is a seven-pole 005 degree error equal ripple filter It utilizes the Kost pulse slimming tech- nique similar to that which is employed on the DP849192 integrated read channel devices The amount of pulse slim- ming is control register selectable in 8 steps up to a maxi- mum of 9 dB measured from the base frequency The band- width of the filter is derived from the XTLIN frequency from this point the b3 dB frequency is selectable via 7 bits in the control register (FILT 3dB 0 – FILT 3dB 6) The data synchronizer section incorporates zero-phase- start (ZPS) and digitally controlled window strobe functions The voltage controlled oscillator (VCO) is fully integrated requiring no external components and provides a wide dy- namic range necessary for zoned data rate applications Data windowing is based on precise VCO duty cycle sym- metry (in contrast to delay line based centering) An internal silicon delay line used to establish the phase detector re- trace angle automatically tracks zoned data recording data rate changes The charge pump output (CPO) and voltage controlled oscillator input (VCOI) are provided as separate pins allowing ample design flexibility in the external loop filter Frequency lock may be employed within the synchro- nization field Charge pump (phase detector) gain may be selected to remain constant or to vary either by a factor of two or four as instructed via the charge pump gain pin (CPGAIN) and a bit in the control register (CPRATIO) The frequency synthesizer section capable of producing a large number of frequencies from a single external refer- ence source generates the write clock and reference fre- quency for the synchronizer This section includes a phase locked loop (PLL) with selectable dividers at the input port and in its feedback loop The values for the dividers are controlled by two control words within the control register The user has full control over both the input (five bit word PDATA6 – PDATA10) and feedback (six bit word PDATA0 – PDATA5) divider selection The feedback divider has an ex- tra bit when compared to previous NSC integrated read channel circuits to improve the resolution of frequency set- ting All blocks within the synthesizer except the RC loop filter are fully integrated The loop filter resides external to the chip giving the user full control over the phase locked loop’s dynamics This device is available in an 80-pin 12 mm x 12 mm PQFP package and operates off of a single a5V supply Features Y Operates at NRZ data rates up to 50 Mbitssec (equiv- alent 23 (17) code data rate) Y Operates with a single a 5V power supply Y Multiple power down modes available with dedicated SLEEP and IDLESERVO power down pins Y Sleep mode included where ICC e 2 mA maximum Y Directly addresses zoned data recording requirements Integrated channel filter with selectable equalization and bandwidth eliminates multiple external filter ele- ments Fully integrated frequency synthesizer on-chip to pro- vide write clock and center frequency for the syn- chronizer Y Selectable delay impedance switch (clamp) at pulse de- tector input for rapid recovery from the write mode Y Pattern insensitive fast AGC for rapid head switch set- tling and embedded servo normalization Y Built-in AGC hold for embedded servo Y Two AGC control voltage pins providedone for servo field and one for data field Y Four gated detectors for quadrature embedded servo information Y Two servo difference amplifiers on-chip http www nationalcom 2 |
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