Electronic Components Datasheet Search |
|
DP84902M Datasheet(PDF) 1 Page - National Semiconductor (TI) |
|
|
DP84902M Datasheet(HTML) 1 Page - National Semiconductor (TI) |
1 / 16 page TLF11963 June 1994 DP84902 17 EncoderDecoder Circuit General Description The DP84902 is designed to perform the encoding and de- coding for disk memory systems It is designed to interface directly with Integrated Read Channel Products (such as National Semiconductor’s DP84910) and with Disk Data Controller Products with a 2-bit NRZ interface (such as Na- tional Semiconductor’s Advanced Disk Controllers) This EncoderDecoder (ENDEC) circuit employs a 23 (17) Run Length Limited (RLL) code type and supports the hard sec- tored format The DP84902 has the option of selecting either TTL or ECL compatible code output to interface with preamplifiers com- monly used in high data rate applications This is accomm- plished by the setting of a bit in the control register The ENDEC also includes write data precompensation con- trol circuitry which detects the need for write precompensa- tion This circuitry issues early and late output signals nec- essary for precompensation The precompensation informa- tion is generated against a 2T pattern The precompensa- tion circuitry can be bypassed by the setting of a bit in the control register A control reigster is included to configure the ENDEC and to select device operation options such as output code inver- sion differential code output bypassing of the encoder and the use of an internal write clock The DP84902 is available in 20-pin SO and 20-pin SSO packages Features Y Operates at 2-bit Non-Return to Zero (NRZ) Data Rates up to 50 Mbitssecond Y Single a5V Power Supply Operation Y Low Power Dissipation when TTL compatible code out- put is selected 150 mW at 50 Mbitssecond NRZ Rate Y TTL Compatible Inputs and Outputs Y ECL Compatible Code Outputs (patented) are control register selectable Y Two-bit NRZ Interface Y Supports Write Data Precompensation with Early and Late output signals Y Selectable use of either an Internal or External Write Clock Y Power Down Mode Included Y DC-Erasure is available to support Analog Flaw Map- ping Testing Y Bypass Mode available which permits Un-Encoded Test Patterns to be issued at the CODEOUT Pin Block Diagram TLF11963 – 1 FIGURE 1 DP84902 ENDEC Block Diagram TRI-STATE is a registered trademark of National Semiconductor Corporation IBM is a registered trademark of International Business Machines Corporation C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
Similar Part No. - DP84902M |
|
Similar Description - DP84902M |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |