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LM4450B Datasheet(PDF) 10 Page - Texas Instruments |
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LM4450B Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 45 page  LM4550B SNAS276G – MAY 2005 – REVISED SEPTEMBER 2015 www.ti.com Electrical Characteristics (continued) The following specifications apply for AVDD = 5V, DVDD = 3.3 V, Fs = 48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for TA= 25°C. The reference for 0 dB is 1 Vrms unless otherwise specified. (1)(2) PARAMETER TEST CONDITIONS MIN TYP(3) MAX(4) UNIT Frequency Response –1-dB Bandwidth 20 kHz DIGITAL TO ANALOG CONVERTERS Resolution 18 Bits Dynamic Range (6) –60-dB Input THD+N, A-Weighted 82 89 dB THD Total Harmonic Distortion VIN = –3 dB, f = 1 kHz, RL = 10 kΩ 0.01% Frequency Response 20-21k Hz Group Delay (6) Sample Freq. = 48 kHz 0.36 1 ms Out of Band Energy (7) -40 dB Stop Band Rejection 70 dB DT Discrete Tones -96 dB ANALOG OUTPUT SECTION AS Step Size 0 dB to –46.5 dB 1.5 dB AM Mute Attenuation(6) 86 dB Headphone Amplifier Total Loopthrough Mode(5), RL = 32 Ω, f = 1 kHz, THD+N 0.02% Harmonic Distortion plus Noise Pout = 50 mW ZOUT Output Impedance(6) HP_OUT_L, HP_OUT_R 0.65 2.75 Ω ZOUT Output Impedance(6) LINE_OUT_L, LINE_OUT_R, MONO_OUT 220 500 Ω DIGITAL I/O(6) VIH High level input voltage 0.65 x DVDD V 0.35 x VIL Low level input voltage V DVDD VOH High level output voltage IO = –2.5 mA. 0.90 x DVDD V 0.10 x VOL Low level output voltage IO = 2.5 mA. V DVDD IL Input Leakage Current AC Link inputs ±10 µA IL Tri state Leakage Current High impedance AC Link outputs ±10 µA Cin AC-Link I/O capacitance SDout, BitClk, SDin, Sync, Reset# only 4 7.5 pF IDR Output drive current AC Link outputs 5 mA (7) Out of band energy is measured from 28.8 kHz to 100 kHz relative to a 1 Vrms DAC output. 7.6 Timing Requirements MIN NOM MAX UNIT DIGITAL TIMING SPECIFICATIONS(1) 12.2 FBC BIT_CLK frequency MHz 88 TBCP BIT_CLK period 81.4 ns TCH BIT_CLK high Variation of BIT_CLK duty cycle from 50% ±20% FSYNC SYNC frequency 48 kHz TSP SYNC period 20.8 µs TSH SYNC high pulse width 1.3 µs TSL SYNC low pulse width 19.5 µs TDSETUP Setup Time for codec data input SDATA_OUT to falling edge of BIT_CLK 10 3.5 ns Hold time of SDATA_OUT from falling edge of TDHOLD Hold Time for codec data input 10 5.3 ns BIT_CLK(1) TSSETUP Setup Time for codec SYNC input SYNC to falling edge of BIT_CLK (1) 10 3.8 ns TSHOLD Hold Time for codec SYNC input Hold time of SYNC from falling edge of BIT_CLK 10 ns (1) These specifications are ensured by design and characterization; they are not production tested. 10 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: LM4550B |
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