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LM4450B Datasheet(PDF) 7 Page - Texas Instruments |
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LM4450B Datasheet(HTML) 7 Page - Texas Instruments |
7 / 45 page LM4550B www.ti.com SNAS276G – MAY 2005 – REVISED SEPTEMBER 2015 Pin Functions (continued) PIN I/O DESCRIPTION NAME NO. AC Link frame marker and Warm Reset This input defines the boundaries of AC Link frames. Each frame lasts 256 periods of BIT_CLK. In normal operation SYNC is a 48 kHz positive pulse with a duty cycle of 6.25% (16/256). SYNC is sampled on the falling edge of BIT_CLK and the codec takes the first positive sample of SYNC as SYNC 10 I defining the start of a new AC Link frame. If a subsequent SYNC pulse occurs within 255 BIT_CLK periods of the frame start it will be ignored. SYNC is also used as an active high input to perform an (asynchronous) Warm Reset. Warm Reset is used to clear a power-down state on the codec AC Link interface. Cold Reset This active low signal causes a hardware reset which returns the control registers and all internal circuits to their default conditions. RESET# MUST be used to initialize the LM4550B after Power On RESET# 11 I when the supplies have stabilized. Cold Reset also clears the codec from both ATE and Vendor test modes. In addition, while active, it switches the PC_BEEP mono input directly to both channels of the LINE_OUT stereo output. Codec Identity ID1# and ID0# determine the Codec Identity for multiple codec use. The Codec Identity configures the codec in either Primary or one of three Secondary Codec modes. These Identity pins are of inverted polarity relative to the Codec Identity bits ID1, ID0 (bits D15, D14) in the read-only Extended Audio ID ID0# 45 I register, 28h. If the ID0# pin (pin 45) is connected to ground then the ID0 bit (D14, reg 28h) will be set to 1. Similarly, connection to DVDD will set the ID0 bit to 0. If left open (NC), ID0# is pulled high by an internal pullup resistor. The Codec Identity bits are also used in the Chain-In Control register, 74h. See the register description and the CIN pin description for details. Codec Identity ID1# and ID0# determine the codec address for multiple codec use. The Codec Identity configures the codec in either Primary or one of three Secondary Codec modes. These Identity pins are of inverted polarity relative to the Codec Identity bits ID1, ID0 (bits D15, D14) in the read-only Extended Audio ID ID1# 46 I register, 28h. If the ID1# pin (pin 46) is connected to ground then the ID1 bit (D15, reg 28h) will be set to 1. Similarly, connection to DVDD will set the ID1 bit to 0. If left open (NC), ID1# is pulled high by an internal pullup resistor. The Codec Identity bits are also used in the Chain-In Control register, 74h. See the register description and the CIN pin description for details. External Amplifier Power-Down control signal This output is set by the EAPD bit (bit D15) in the Power-down Control/Status register, 26h. As with EAPD 47 O the other logic outputs, the output voltage is set by DVDD. This pin is intended to be connected to the shutdown pin on an external power amplifier. For normal operation the default value of EAPD = 0 will enable the external amplifier allowing an input on PC_BEEP to be heard during Cold Reset. Chain In The codec can be instructed to disconnect its own SDATA_IN signal and instead pass the signal on CIN through to the SDATA_IN output pin. This is achieved by changing the value of the two LSBs of the Chain-In Control register (74h) so that they differ from the Codec Identity bits ID1, ID0. Those two LSBs default to the value of the Codec Identity bits following Cold Reset thereby disabling the Chain In CIN 48 I feature. Chain In can also be disabled by reading the Codec Identity from the Extended Audio ID register (28h) and writing the value back into register 74h LSBs. The Codec Identity bits are determined by the input pins ID1#, ID0#. CIN can be left open (NC) provided that the chain feature is disabled. When the chain feature is used, CIN should always be driven. Either connect the SDATA_IN pin from another codec or else ground CIN to prevent the possibility of floating the SDATA_IN signal at the controller. POWER SUPPLIES AND REFERENCES AVDD1 25 I Analog supply AVSS1 26 I Analog ground AVDD2 38 I Analog supply 2 AVSS2 42 I Analog ground 2 DVDD1 1 I Digital supply DVDD2 9 I Digital supply DVSS1 4 I Digital ground DVSS2 7 I Digital ground Nominal 2.2-V internal reference VREF 27 O Not intended to sink or source current. Use short traces to bypass (3.3 µF, 0.1 µF) this pin to maximize codec performance. See text. Nominal 2.2-V reference output VREF_OUT 28 O Can source up to 5 mA of current and can be used to bias a microphone. Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LM4550B |
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