SCAN921226 datasheet(7/21 Pages) NSC

Part #	SCAN921226

Description	30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST

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Manufacturer	NSC [National Semiconductor (TI)]

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Serializer Switching Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

t

DIS

DIN (0-9) Setup to TCLK

R

L =27Ω,

C

L=10pF to GND

Figure 7

0ns

t

DIH

DIN (0-9) Hold from

TCLK

4.0

ns

t

HZD

DO ± HIGH to

TRI-STATE Delay

R

L =27Ω,

C

L=10pF to GND

Figure 8

(Note 5)

310

ns

t

LZD

DO ± LOW to

TRI-STATE Delay

310

ns

t

ZHD

DO ± TRI-STATE to

HIGH Delay

510

ns

t

ZLD

DO ± TRI-STATE to

LOW Delay

6.5

10

ns

t

SPW

SYNC Pulse Width

R

L =27Ω

Figure 10

5*t

TCP

ns

t

PLD

Serializer PLL Lock Time

510*t

TCP

513*t

TCP

ns

t

SD

Serializer Delay

R

L =27Ω, Figure 11

t

TCP+

1.0

t

TCP+

2.5

t

TCP+

3.5

ns

t

DJIT

Deterministic Jitter

R

L =

27

Ω,

C

L=10pF

to GND,

(Note 6)

80 MHz

-130

-40

+60

ps

t

RJIT

Random Jitter

610

ps

(RMS)

Deserializer Timing Requirements for REFCLK

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

t

RFCP

REFCLK Period

12.5

T

33.3

ns

t

RFDC

REFCLK Duty Cycle

30

50

70

%

t

RFCP /tTCP

Ratio of REFCLK to TCLK

95

1

105

t

RFTT

REFCLK Transition Time

3

6

ns

Deserializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Pin/Freq.

Min

Typ

Max

Units

t

RCP

Receiver out Clock

Period

t

RCP =tTCP

Figure 11

RCLK

12.5

33.3

ns

t

CLH

CMOS/TTL Low-to-High

Transition Time

CL=15pF

Figure 5

Rout(0-9),

LOCK,

RCLK

1.2

4

ns

t

CHL

CMOS/TTL High-to-Low

Transition Time

1.1

4

ns

t

DD

Deserializer Delay

Figure 12

All Temp./ All Freq.

1.75*t

RCP+1.25

1.75*t

RCP+5.0

1.75*t

RCP+8.5

ns

Room Temp./3.3V/30MHz

1.75*t

RCP+2.25

1.75*t

RCP+5.0

1.75*t

RCP+8.0

ns

Room Temp./3.3V/80MHz

1.75*t

RCP+2.25

1.75*t

RCP+5.0

1.75*t

RCP+8.0

ns

t

ROS

ROUT Data Valid before

Figure 13

RCLK

30MHz

0.4*t

RCP

0.5*t

RCP

ns

RCLK

80MHz

0.35*t

RCP

0.5*t

RCP

ns

t

ROH

ROUT Data valid after

Figure 13

30MHz

−0.4*t

RCP

−0.5*t

RCP

ns

RCLK

80MHz

−0.35*t

RCP

−0.5*t

RCP

ns

t

RDC

RCLK Duty Cycle

45

50

55

%

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