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LM3711 Datasheet(PDF) 2 Page - Texas Instruments |
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LM3711 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 19 page Reset VCC GND WDI MR NC PFI LLO PFO C B A 1 2 3 1 2 3 4 9 5 10 8 7 6 VCC MR PFI WDI NC GND LLO PFO NC Reset LM3710, LM3711 SNVS150E – NOVEMBER 2000 – REVISED MARCH 2013 www.ti.com Connection Diagram Figure 1. VSSOP-10 Figure 2. Top View (looking from the coating side) DSBGA 9 Bump Package PIN DESCRIPTIONS Pin No. Name Function DSBGA VSSOP A1 2 MR Manual-Reset input. When MR is less than VMRT (Manual Reset Threshold) RESET/RESET is engaged. B1 1 VCC Power Supply input. C1 10 RESET Reset Logic Output. Pulses low for tRP (Reset Timeout Period) when triggered, and stays low whenever VCC is below the reset threshold or when MR is below VMRT. It remains low for tRP after either VCC rises above the reset threshold, or after MR input rises above VMRT (LM3710 only). RESET Reset Logic Output. RESET is the inverse of RESET (LM3711 only). C2 8 PFO Power-Fail Logic Output. When PFI is below VPFT, PFO goes low; otherwise, PFO remains high. C3 7 LLO Low-Line Logic Output. Early Power-Fail warning output. Low when VCC falls below VLLOT (Low- Line Output Threshold). This output can be used to generate an NMI (Non-Maskable Interrupt) to provide an early warning of imminent power-failure. B3 5 GND Ground reference for all signals. A3 4 WDI Watchdog Input Transition Monitor: If no transition activity occurs for a period exceeding tWD (Watchdog Timeout Period), reset is engaged. A2 3 PFI Power-Fail Comparator Input. When PFI is less than VPFT (Power-Fail Reset Threshold), the PFO goes low; otherwise, PFO remains high. B2 6, 9 NC No Connect. Test input used at factory only. Leave floating. 2 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LM3710 LM3711 |
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