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DP8422AV-20 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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DP8422AV-20 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 58 page  TLF8588 July 1992 DP8420A21A22A microCMOS Programmable 256k1M4M Dynamic RAM ControllerDrivers General Description The DP8420A21A22A dynamic RAM controllers provide a low cost single chip interface between dynamic RAM and all 8- 16- and 32-bit systems The DP8420A21A22A gen- erate all the required access control signal timing for DRAMs An on-chip refresh request clock is used to auto- matically refresh the DRAM array Refreshes and accesses are arbitrated on chip If necessary a WAIT or DTACK out- put inserts wait states into system access cycles including burst mode accesses RAS low time during refreshes and RAS precharge time after refreshes and back to back ac- cesses are guaranteed through the insertion of wait states Separate on-chip precharge counters for each RAS output can be used for memory interleaving to avoid delayed back to back accesses because of precharge An additional fea- ture of the DP8422A is two access ports to simplify dual accessing Arbitration among these ports and refresh is done on chip Features Y On chip high precision delay line to guarantee critical DRAM access timing parameters Y microCMOS process for low power Y High capacitance drivers for RAS CAS WE and DRAM address on chip Y On chip support for nibble page and static column DRAMs Y Byte enable signals on chip allow byte writing in a word size up to 32 bits with no external logic Y Selection of controller speeds 20 MHz and 25 MHz Y On board Port APort B (DP8422A only)refresh arbitra- tion logic Y Direct interface to all major microprocessors (applica- tion notes available) Y 4 RAS and 4 CAS drivers (the RAS and CAS configura- tion is programmable) of Pins of Address Largest Direct Drive Access Control (PLCC) Outputs DRAM Memory Ports Possible Capacity Available DP8420A 68 9 256 kbit 4 Mbytes Single Access Port DP8421A 68 10 1 Mbit 16 Mbytes Single Access Port DP8422A 84 11 4 Mbit 64 Mbytes Dual Access Ports (A and B) Block Diagram DP8420A21A22A DRAM Controller TLF8588 – 5 FIGURE 1 TRI-STATE is a registered trademark of National Semiconductor Corporation Staggered RefreshTM is a trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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