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DP8464B Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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DP8464B Datasheet(HTML) 5 Page - National Semiconductor (TI) |
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5 / 26 page  Circuit Operation (Continued) of a differential comparator with hysteresis and a D flip-flop The hysteresis for this comparator is externally set via the Set Hysteresis pin In order to have data out the input am- plitude must first cross the hysteresis level which will change the logic level on the D input of the flip-flop The peak of the input signal will generate a pulse out of the differentiator and bi-directional one shot This pulse will clock the new data at the D input through to the output In this way when the differentiator is responding to noise at the baseline the output of the D flop is not changing since the logic level into the D input has not changed The com- parator circuitry is therefore a gating channel which pre- vents any noise near the baseline from contaminating the data The amount of hysteresis is twice the DC voltage on the Set Hysteresis pin For instance if the voltage on the Set Hysteresis pin is 03V the differential AC signal across the Gate Channel Input must be larger than 06V before the output of the comparator will change states In this case the hysteresis is 30% of a 2V peak to peak differential sig- nal at the gate channel input Connection Diagrams Dual-In-Line (DIP) Package TLF5283 – 2 Top View Order Number DP8464BN-3 or DP8464BN-2 See NS Package N24C Plastic Chip Carrier (PCC) Package TLF5283 – 30 Order Number DP8464BV-3 DP8464BV-2 or DP8464BV-1 See NS Package V28A 5 |
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