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DP8422V-33 Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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DP8422V-33 Datasheet(HTML) 7 Page - National Semiconductor (TI) |
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7 / 60 page  20 Signal Descriptions (Continued) Pin Device (If Not Input Description Name Applicable to All) Output 25 PORT B ACCESS SIGNALS AREQB DP8422VT22 I PORT B ACCESS REQUEST This input asserted will latch the row column and bank address if programmed and requests an access to take place for Port B If the only access can take place RAS will assert immediately If the access has to be delayed RAS will assert as soon as possible from a positive edge of CLK ATACKB DP8422VT22 O ADVANCED TRANSFER ACKNOWLEDGE PORT B This output is asserted when the access RAS is asserted for a Port B access This signal can be used to generate only the appropriate DTACK or WAIT type signal for Port B’s CPU or bus 26 COMMON DUAL PORT SIGNALS GRANTB DP8422VT22 O GRANT B This output indicates which port is currently granted access to the DRAM array When GRANTB is asserted Port B has access to the array When GRANTB is only negated Port A has access to the DRAM array This signal is used to multiplex the signals R0 – 8 9 10 C0 – 8 9 10 B0 – 1 WIN LOCK and ECAS0 – 3 to the DP8422V when using dual accessing LOCK DP8422VT22 I LOCK This input can be used by the currently granted port to ‘‘lock out’’ the other port from the DRAM array by inserting wait states into the locked out port’s access only cycle until LOCK is negated 27 POWER SIGNALS AND CAPACITOR INPUT VCC I POWER Supply Voltage GND I GROUND Supply Voltage Reference CAP I CAPACITOR This input is used by the internal PLL for stabilization The value of the ceramic capacitor should be 01 mF and should be connected between this input and ground 28 CLOCK INPUTS There are two clock inputs to the DP8420V21V22V DP84T22 CLK and DELCLK These two clocks may both be tied to the same clock input or they may be two separate clocks running at different frequencies asynchronous to each other CLK I SYSTEM CLOCK This input may be in the range of 0 Hz up to 33 MHz (up to 25 MHz in the DP84T22V) This input is generally a constant frequency but it may be controlled externally to change frequencies or perhaps be stopped for some arbitrary period of time This input provides the clock to the internal state machine that arbitrates between accesses and refreshes This clock’s positive edges and negative levels are used to extend the WAIT (DTACK) signals This clock is also used as the reference for the RAS precharge time and RAS low time during refresh All Port A and Port B accesses are assumed to be synchronous to the system clock CLK DELCLK I DELAY LINE CLOCK The clock input DELCLK may be in the range of 6 MHz to 20 MHz and should be a multiple of 2 (ie 6 8 10 12 14 16 18 20 MHz) to have the DP8420V21V22V DP84T22 switching characteristics hold If DELCLK is not one of the above frequencies the accuracy of the internal delay line will suffer This is because the phase locked loop that generates the delay line assumes an input clock frequency of a multiple of 2 MHz For example if the DELCLK input is at 7 MHz and we choose a divide by 3 (program bits C0 – 2) this will produce 2333 MHz which is 16667% off of 2 MHz Therefore the DP8420V21V22V DP84T22 delay line would produce delays that are shorter (faster delays) than what is intended If divide by 4 was chosen the delay line would be longer (slower delays) than intended (175 MHz instead of 2 MHz) (See Section 9 for more information) This clock is also divided to create the internal refresh clock 7 |
Similar Part No. - DP8422V-33 |
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Similar Description - DP8422V-33 |
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