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SN65HVD34D Datasheet(PDF) 5 Page - Texas Instruments |
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SN65HVD34D Datasheet(HTML) 5 Page - Texas Instruments |
5 / 42 page SN65HVD30, SN65HVD31, SN65HVD32 SN65HVD33, SN65HVD34, SN65HVD35 www.ti.com SLLS665K – SEPTEMBER 2005 – REVISED OCTOBER 2015 Pin Functions PIN TYPE DESCRIPTION D D RHL NAME (8-Pins) (14-Pins) (20-Pins) A 8 12 18 Bus input Receiver input (complementary to B) B 7 11 17 Bus input Receiver input (complementary to A) D 3 5 7 Digital input Driver data input DE — 4 6 Digital input Driver enable, active high Reference GND 4 6, 7 10, 11 Local device ground potential 2, 5, 8, NC — 1, 8 9, 12, No connect No connect; must be left floating 13, 16, 19 R 2 2 3 Digital output Receive data output RE — 3 4 Digital output Receiver enable, active low VCC 1 13, 14 1, 20 Supply 3-V to 3.6-V supply Y 5 9 14 Bus output Driver output (complementary to Z) Z 6 10 15 Bus output Driver output (complementary to Y) 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range unless otherwise noted (1) (2) MIN MAX UNIT VCC Supply voltage –0.3 6 V V(A), V(B), Voltage at any bus terminal (A, B, Y, Z) –9 14 V V(Y), V(Z) V(TRANS) Voltage input, transient pulse through 100 Ω. See Figure 28 (A, B, Y, Z)(3) –50 50 V VI Input voltage (D, DE, RE) –0.5 7 V IO Output current (receiver output only, R) 11 mA Tstg Storage Temperature 125 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) This tests survivability only and the output state of the receiver is not specified. 7.2 ESD Ratings VALUE UNIT Bus pins and GND ±16000 Human body model (HBM), per ANSI/ESDA/JEDEC Electrostatic JS-001(1) V(ESD) All pins ±4000 V discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: SN65HVD30 SN65HVD31 SN65HVD32 SN65HVD33 SN65HVD34 SN65HVD35 |
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