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S6E2C49J0AGB10000 Datasheet(PDF) 4 Page - Texas Instruments |
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S6E2C49J0AGB10000 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 193 page  Document Number: 002-04986 Rev.*A Page 4 of 193 S6E2C4 Series Programmable Cyclic Redundancy Check (PRGCRC) Accelerator The CRC accelerator helps a verify data transmission or storage integrity. CCITT CRC16, IEEE-802.3 CRC32 and generating polynomial are supported. CCITT CRC16 generator polynomial: 0x1021 IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7 Generating polynomial SD Card Interface It is possible to use the SD card that conforms to the following standards. Part 1 Physical Layer Specification version 3.01 Part E1 SDIO Specification version 3.00 Part A2 SD Host Controller Standard Specification version 3.00 1-bit or 4-bit data bus I 2S (Inter-IC Sound Bus) Interface (TX x 1 channel, RX x 1 channel) Supports three transfer protocols I 2S Left justified DSP mode Separate clock generation block for flexible system integration options Master/slave mode selectable RX Only, TX Only or TX and RX simultaneous operation selectable Word length is programmable from 7-bits to 32 bits RX/TX FIFO integrated (RX: 66 words x 32-bits, TX: 66 words x 32-bits) DMA, interrupts, or polling based data transfer supported High-Speed Quad SPI Up to 66 MHz clock rates for very fast data transfers to and from SPI compatible devices. Up to 256 Mbytes of memory mapped address space. Single data rate (SDR) Supports single, dual, and quad data modes Built-in direct mode and command sequencer mode Direct mode: Access by use of transmission FIFO/reception FIFO (up to16 word x 32 bit) Command sequencer mode: Automatic access assigned to external device area. Clock and Reset Clocks Five clock sources (two external oscillators, two internal CR oscillators, and Main PLL) that are dynamically selectable. Main clock: 4 MHz to 48 MHz Sub clock: 32.768 kHz High-speed internal CR clock: 4 MHz Low-speed internal CR clock: 100 kHz Main PLL Clock Resets Reset requests from INITX pin Power on reset Software reset Watchdog timer reset Low-voltage detector reset Clock supervisor reset Clock Supervisor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks. External OSC clock failure (clock stop) is detected, reset is asserted. External OSC frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series include two-stage monitoring of voltage on the VCC pins. when the voltage falls below the voltage that has been set, the low-voltage detector function generates an interrupt or reset. LVD1: error reporting via interrupt LVD2: auto-reset operation Low-power Consumption Mode Six low power consumption modes are supported. Sleep Timer RTC Stop Deep standby RTC (selectable from with/without RAM retention) Deep standby stop (selectable from with/without RAM retention) Peripheral Clock Gating The system can reduce the current consumption of the total system with gating the operation clocks of peripheral functions not used. |
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