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DP8431V Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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DP8431V Datasheet(HTML) 7 Page - National Semiconductor (TI) |
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7 / 56 page  20 Signal Descriptions (Continued) Pin Device (If not Input Description Name Applicable to All) Output 26 COMMON DUAL PORT SIGNALS GRANTB DP8432V O GRANT B This output indicates which port is currently granted access to the DRAM array When GRANTB is asserted Port B has access to the array When GRANTB is only negated Port A has access to the DRAM array This signal is used to multiplex the signals R0 – 8 9 10 C0 – 8 9 10 B0 – 1 WIN LOCK and ECAS0 – 3 to the DP8432V when using dual accessing LOCK DP8432V I LOCK This input can be used by the currently granted port to ‘‘lock out’’ the other port from the DRAM array by inserting wait states into the locked out port’s access only cycle until LOCK is negated 27 POWER SIGNALS AND CAPACITOR INPUT VCC I POWER Supply Voltage GND I GROUND Supply Voltage Reference CAP I CAPACITOR This input is used by the internal PLL for stabilization The value of the ceramic capacitor should be 01 mF and should be connected between this input and ground 28 CLOCK INPUTS There are two clock inputs to the DP8430V31V32V CLK and DELCLK These two clocks may both be tied to the same clock input or they may be two separate clocks running at different frequencies asynchronous to each other CLK I SYSTEM CLOCK This input may be in the range of 0 Hz up to 25 MHz This input is generally a constant frequency but it may be controlled externally to change frequencies or perhaps be stopped for some arbitrary period of time This input provides the clock to the internal state machine that arbitrates between accesses and refreshes This clock’s positive edges and negative levels are used to extend the WAIT (DTACK) signals Ths clock is also used as the reference for the RAS precharge time and RAS low time during refresh All Port A and Port B accesses are assumed to be synchronous to the system clock CLK DELCLK I DELAY LINE CLOCK The input frequency to DELCLK should be in the range of 12 MHz to 40 MHz This frequency will be internally divided by choosing a divisor when programming the part The result of the division should be a frequency of 2 MHz This is because the Phase Lock Loop that generates the delay line assumes an input clock frequency of 2 MHz If after dividing DELCLK by one of the internal divisors (6 8 10 12 14 16 18 or 20) the resulting frequency is not 2 MHz the delay line will suffer For example if the DELCLK frequency is 18 MHz and a divide by 8 is chosen programming bits C0 – 2 the resulting frequency will be 225 which is 125% off of 2 MHz Therefore the DP8430V31V32V will produce delays that are shorter (faster delays) than what is intended On the other hand if divide by 10 was chosen the resulting frequency will be 18 MHz this frequency will produce delays that are longer (slower delays) than intended This clock is also divided to create the internal refresh clock 7 |
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Similar Description - DP8431V |
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