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PRELIMINARY
CY7C1484V33
CY7C1485V33
Document #: 38-05285 Rev. *A
Page 5 of 29
Pin Configurations (continued)
CY7C1484V33 (2M × 36)–11 × 15 FBGA
165-ball Bump FBGA (This package is offered on an opportunity basis)
CY7C1485V33 (4M × 18)–11 × 15 FBGA
234
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC
NC
NC
NC
DPb
NC
DQb
ACE1
NC
CE3
BWb
BWE
ACE2
NC
DQb
DQb
MODE
NC
DQb
DQb
NC
NC
NC
A
A
VDDQ
NC
BWa
CLK
GW
VSS
VSS
VSS
VSS
VDDQ
VSS
VDD
VSS
VSS
VSS
A
VSS
VSS
VSS
VSS
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
A
A
VDD
VSS
VDD
VSS
VSS
VDDQ
VDD
VSS
VDD
VSS
VDD
VSS
VSS
VSS
VDD
VDD
VSS
VDD
VSS
VSS
NC
TCK
A0
VSS
ATDI
ATMS
DQb
VSS
NC
VSS
DQb
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A1
DQb
NC
NC
NC
VDDQ
VSS
89
10
11
A
ADV
A
ADSC
A
OE
ADSP
A
144M
VSS
VDDQ
NC
DPa
VDDQ
VDD
NC
DQa
DQa
NC
NC
NC
DQa
NC
VDD
VDDQ
VDD
VDDQ
DQa
VDD
NC
VDD
NC
VDD
VDDQ
DQa
VDDQ
VDD
VDD
VDDQ
VDD
VDDQ
NC
VDDQ
A
A
VSS
AA
AA
DQa
NC
NC
ZZ
DQa
NC
NC
DQa
A
VDDQ
2
3
456
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC
NC
DPc
DQc
DPd
NC
DQd
ACE1
BWb
CE3
BWc
BWE
ACE2
DQc
DQd
DQd
MODE
NC
DQc
DQc
DQd
DQd
DQd
A
A
VDDQ
BWd
BWa
CLK
GW
VSS
VSS
VSS
VSS
VDDQ
VSS
VDD
VSS
VSS
VSS
A
VSS
VSS
VSS
VSS
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
A
A
VDD
VSS
VDD
VSS
VSS
VDDQ
VDD
VSS
VDD
VSS
VDD
VSS
VSS
VSS
VDD
VDD
VSS
VDD
VSS
VSS
NC
TCK
A0
VSS
ATDI
ATMS
DQc
VSS
DQc
VSS
DQc
DQc
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A1
DQd
DQd
NC
NC
VDDQ
VSS
89
10
11
A
ADV
A
ADSC
NC
OE
ADSP
A144M
VSS
VDDQ
NC
DPb
VDDQ
VDD
DQb
DQb
DQb
NC
DQb
NC
DQa
DQa
VDD
VDDQ
VDD
VDDQ
DQb
VDD
NC
VDD
DQa
VDD
VDDQ
DQa
VDDQ
VDD
VDD
VDDQ
VDD
VDDQ
DQa
VDDQ
A
A
VSS
AA
AA
DQb
DQb
DQb
ZZ
DQa
DQa
DPa
DQa
A
VDDQ
Pin Definitions
Pin Name
I/O
Pin Description
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0]
feed the two-bit counter.
BWa
BWb
BWc
BWd
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d and
BWE).
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