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DP8420AV-25 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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DP8420AV-25 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
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6 / 58 page  20 Signal Descriptions (Continued) Pin Device (If not Input Description Name Applicable to All) Output 23 REFRESH SIGNALS RFIP O REFRESH IN PROGRESS This output is asserted prior to a refresh cycle and is negated when all the RAS outputs are negated for that refresh RFSH I REFRESH This input asserted with DISRFRSH already asserted will request a refresh If this input is continually asserted the DP8420A21A22A will perform refresh cycles in a burst refresh fashion until the input is negated If RFSH is asserted with DISRFSH negated the internal refresh address counter is cleared (useful for burst refreshes) DISRFSH I DISABLE REFRESH This input is used to disable internal refreshes and must be asserted when using RFSH for externally requested refreshes 24 PORT A ACCESS SIGNALS ADS I ADDRESS STROBE or ADDRESS LATCH ENABLE Depending on programming this input can function as ADS or ALE In mode 0 the input functions as ALE and (ALE) I when asserted along with CS causes an internal latch to be set Once this latch is set an access will start from the positive clock edge of CLK as soon as possible In Mode 1 the input functions as ADS and when asserted along with CS causes the access RAS to assert if no other event is taking place If an event is taking place RAS will be asserted from the positive edge of CLK as soon as possible In both cases the low going edge of this signal latches the bank row and column address if programmed to do so CS I CHIP SELECT This input signal must be asserted to enable a Port A access AREQ I ACCESS REQUEST This input signal in Mode 0 must be asserted some time after the first positive clock edge after ALE has been asserted When this signal is negated RAS is negated for the access In Mode 1 this signal must be asserted before ADS can be negated When this signal is negated RAS is negated for the access WAIT O WAIT or DTACK This output can be programmed to insert wait states into a CPU access cycle With R7 negated during programming the output will function as a (DTACK)O WAIT type output In this case the output will be active low to signal a wait condition With R7 asserted during programming the output will function as DTACK In this case the output will be negated to signify a wait condition and will be asserted to signify the access has taken place Each of these signals can be delayed by a number of positive clock edges or negative clock levels of CLK to increase the microprocessor’s access cycle through the insertion of wait states WAITIN I WAIT INCREASE This input can be used to dynamically increase the number of positive clock edges of CLK until DTACK will be asserted or WAIT will be negated during a DRAM access 6 |
Similar Part No. - DP8420AV-25 |
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Similar Description - DP8420AV-25 |
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