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CDCM1804RGETG4 Datasheet(PDF) 1 Page - Texas Instruments |
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CDCM1804RGETG4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 24 page www.ti.com FEATURES VSS(1) S0 VDD1 Y1 Y1 VDD1 VDD3 18 17 16 15 14 13 1 2 3 4 5 6 EN VDDPECL IN IN VDDPECL VBB 24 23 22 21 20 19 7 8 9 10 11 12 RGE PACKAGE (TOP VIEW) (1) Thermal pad must be connected to VSS. P0024-01 DESCRIPTION (1) Thermal pad must be connected to VSS. P0025-01 18 17 16 15 14 13 S0 VDD1 Y1 Y1 VDD1 VDD3 1 2 3 4 5 6 EN VDDPECL IN IN VDDPECL VBB VSS(1) RTH PACKAGE (TOP VIEW) CDCM1804 SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER The CDCM1804 is characterized for operation from –40 °C to 85°C. • Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs and For use in single-ended driver applications, the CDCM1804 also provides a VBB output terminal that One LVCMOS Single-Ended Output can be directly connected to the unused input as a • Programmable Output Divider for Two common-mode voltage reference. LVPECL Outputs and LVCMOS Output • Low-Output Skew 15 ps (Typical) for Clock-Distribution Applications for LVPECL Outputs; 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise • VCC Range 3 V–3.6 V • Signaling Rate Up to 800-MHz LVPECL and 200-MHz LVCMOS • Differential Input Stage for Wide Common-Mode Range • Provides VBB Bias Voltage Output for Single-Ended Input Signals • Receiver Input Threshold ±75 mV • 24-Terminal QFN Package (4 mm × 4 mm) • Accepts Any Differential Signaling: LVDS, HSTL, CML, VML, SSTL-2, and Single-Ended: LVTTL/LVCMOS The CDCM1804 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0], with mini- mum skew for clock distribution. The CDCM1804 is specifically designed for driving 50- Ω transmission lines. Additionally, the CDCM1804 offers a single-ended LVCMOS output Y3. This output is delayed by 1.6 ns over the three LVPECL output stages to minimize noise impact during signal tran- sitions. The CDCM1804 has three control terminals, S0, S1, and S2, to select different output mode settings. The S[2:0] terminals are 3-level inputs and therefore allow up to 33 = 27 combinations. Additionally, an enable terminal (EN) is provided to disable or enable all outputs simultaneously. The EN terminal is a 3-level input as well and extends the number of settings to 2 × 27 = 54. See Table 1 for details. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2003–2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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