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SN65LVDS150PWR Datasheet(PDF) 2 Page - Texas Instruments |
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SN65LVDS150PWR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 18 page www.ti.com DESCRIPTION (CONTINUED) BLOCK DIAGRAM Frequency Phase Detector VCO Divide by M M1 M2 M3 M4 M5 LVO MCO+ MCO– LCRO+ LCRO– CRI+ CRI– BSEL EN LCRO_EN Ref. Gen. VT SN65LVDS150 SLLS443 – DECEMBER 2000 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. The multiplied clock output (MCO) is an LVDS differential signal used to drive the high-speed shift registers in either the SN65LVDS151 serializer-transmitter or the SN65LVDS152 receiver-deserializer. The link clock reference output (LCRO) is an LVDS differential signal provided to the SN65LVDS151 serializer-transmitter for transmission over the link. An internal power on reset and an enable input (EN) control the operation of the SN65LVDS150. When VCC is below 1.5 V, or when EN is low, the device is in a low power disabled state and the MCO and LCRO differential outputs are in a high-impedance state. When VCC is above 3 V and EN is high, the device and the two differential outputs are enabled and operating to specifications. The link clock reference output enable input (LCRO_EN) is used to turn off the LCRO output when it is not being used. A band select input (BSEL) is used to optimize the VCO performance as a function of M-clock frequencies and M multiplier that is being used: The fmax parameter in the switching characteristic table includes details on the MCO frequency and choices of BSEL and M. 2 Submit Documentation Feedback |
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