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SN65LVP20DRFT Datasheet(PDF) 4 Page - Texas Instruments

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Part # SN65LVP20DRFT
Description  LVPECL AND LVDS REPEATER/TRANSLATOR WITH ENABLE
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN65LVP20DRFT Datasheet(HTML) 4 Page - Texas Instruments

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SWITCHING CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
NC
1
A
2
3
B
5
EN
V BB
Z
Y
4
6
7
VCC
8
GND
9
D.U.T.
VIA
VIB
VCC − 2 V
50
50
S1
IIA
IIB
+
+
VOY
VOZ
VI
II
+
VBB
IBB
IOZ
IOY
VCC
ICC
+
VOC
CL
SN65LVDS20
SN65LVP20
SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
Differential propagation delay time,
tPLH
300
450
630
low-to-high-level output
Differential propagation delay time,
See Figure 2 and Figure 4
ps
tPHL
300
450
630
high-level-to-low-level output
tSK(P)
Pulse skew, |tPLH - tPHL|
20
VCC = 3.3 V
80
tSK(PP)
Part-to-part skew (2)
ps
VCC = 2.5 V
130
LVDS, See Figure 2 and Figure 4
85
115
tr
20%-to-80% differential signal rise time
ps
LVPECL, See Figure 2 and Figure 4
92
120
LVDS, See Figure 2 and Figure 4
85
115
tf
20%-to-80% differential signal fall time
ps
LVPECL, See Figure 2 and Figure 4
92
120
tjit(per)
RMS period jitter(3)
2
3
2-GHz 50%-duty-cycle square-wave input,
ps
See Figure 5
tjit(cc)
Peak cycle-to-cycle jitter (4)
13
16
LVDS; 4 Gbps PRBS, 223- 1 run length,
tjit(p-p)
Peak-to-peak jitter
37
45
ps
See Figure 5
155.52 MHz
0.62
tjit(ph)
Intrinsic phase jitter
ps
622.08 MHz
0.14
Propagation delay time,
tPHZ
30
high-level-to-high-impedance output
Propagation delay time,
tPLZ
30
low-level-to-high-impedance output
See Figure 2 and Figure 6
ns
Propagation delay time,
tPZH
30
high-impedance-to-high-level output
Propagation delay time,
tPZL
30
high-impedance-to-low-level output
(1)
Typical values are at room temperature and with a VCC of 3.3 V.
(2)
Part-to-part skew is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3)
Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles.
(4)
Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles, over a random sample of 1,000 adjacent cycle
pairs.
(1)
CL is the instrumentation and test fixture capacitance.
(2)
S1 is open for the SN65LVDS20 and closed for the SN65LVP20.
Figure 2. Output Voltage Test Circuit and Voltage and Current Definitions
4


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