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Signaling Rate − Mbps

0

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Clock Frequency − MHz

SN65LVDS108

SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005

TYPICAL CHARACTERISTICS (continued)

P-P EYE-PATTERN JITTER

vs

PRBS SIGNALING RATE

100-

Ω loads, worst-case output, supply decoupled with 0.1-µF and 0.001-µF ceramic 0603-style capacitors 1 cm from

the device.

Figure 10.

P-P PERIOD JITTER

vs

CLOCK FREQUENCY

NOTES: Input: 50% duty cycle square wave with period jitter < 9 ps at 100 MHz, all outputs enabled and loaded with

differential 100-

Ω loads,worst-case output, supply decoupled with 0.1-µF and 0.001- µF ceramic 0603-style capacitors

1 cm from the device.

Figure 11.

9