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SN65LV1224B-EP Datasheet(PDF) 10 Page - Texas Instruments |
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SN65LV1224B-EP Datasheet(HTML) 10 Page - Texas Instruments |
10 / 25 page www.ti.com SERIALIZER TIMING REQUIREMENTS FOR TCLK SERIALIZER SWITCHING CHARACTERISTICS DESERIALIZER TIMING REQUIREMENTS FOR REFCLK SN65LV1023A-EP SN65LV1224B-EP SGLS358 – SEPTEMBER 2006 over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tTCP Transmit clock period 15.15 T 100 ns tTCIH Transmit clock high time 0.4T 0.5T 0.6T ns tTCIL Transmit clock low time 0.4T 0.5T 0.6T ns tt(CLK) TCLK input transition time 3 6 ns tJIT TCLK input jitter See Figure 19 150 ps (RMS) Frequency tolerance –100 +100 ppm over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tTLH(L) LVDS low-to-high transition time RL = 27 Ω, CL = 10 pF to GND, See 0.2 ns Figure 6 tLTHL(L) LVDS high-to-low transition time 0.25 ns tsu(DI) DIN0–DIN9 setup to TCLK RL = 27 Ω, CL = 10 pF to GND, See 0.5 ns Figure 9 tsu(DI) DIN0–DIN9 hold from TCLK 4 ns td(HZ) DO ± high-to-high impedance state RL = 27 Ω, CL = 10 pF to GND, See 2.5 delay Figure 10 td(LZ) DO ± low-to-high impedance state 2.5 delay ns td(ZH) DO ± high-to-high impedance 5 state-to-high delay td(ZL) DO ± high-to-high impedance 6.5 state-to-low delay tw(SPW) SYNC pulse duration RL = 27 Ω, See Figure 12 6 ×t TCP ns t(PLD) Serializer PLL lock time 1026 ×t TCP ns td(S) Serializer delay RL = 27 Ω, See Figure 13 tTCP tTCP+2 tTCP+3 ns tDJIT Deterministic jitter RL = 27 Ω, C L = 10 pF to GND 230 ps 150 tRJIT Random jitter RL = 2.7 Ω, C L = 10 pF to GND 10 ps (RMS) over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tRFCP REFCLK period 15.15 T 100 ns tRFDC REFCLK duty cycle 30% 50% 70% tt(RF) REFCLK transition time 3 6 ns Frequency tolerance –100 +100 ppm 10 Submit Documentation Feedback |
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