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SN65LV1021DBG4 Datasheet(PDF) 8 Page - Texas Instruments |
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SN65LV1021DBG4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 22 page www.ti.com SERIALIZER TIMING REQUIREMENTS FOR TCLK SN65LV1021 SN65LV1212 SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) over recommended operating supply and temperature ranges (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOZ High-impedance output current PWRDN or REN = 0.8 V, VOUT = 0 V or VCC -10 ±1 10 µA SERIALIZER LVDS DC SPECIFICATIONS (apply to pins DO+ and DO-) VOD Output differential voltage (DO+)-(DO-) 350 400 mV ∆V OD Output differential voltage unbalance 35 mV RL = 27 Ω, See Figure 18 VOS Offset voltage 1.1 1.2 1.3 V ∆V OS Offset voltage unbalance 35 mV IOS Output short circuit current D0 = 0 V, DINx = high, PWRDN and DEN = 2.4 V -10 -90 mA IOZ High-impedance output current PWRDN or DEN = 0.8 V, DO = 0 V or VCC -10 ±1 10 µA IOX Power-off output current VCC = 0 V, DO = 0 V or VCC -20 ±1 20 µA DESERIALIZER LVDS DC SPECIFICATIONS (apply to pins RI+ and RI-) VTH Differential threshold high voltage VCM = 1.1 V 50 mV VTL Differential threshold low voltage -50 mV VIN = 2.4 V, VCC = 3.6 V or 0 V -10 ±1 15 IIN Input current µA VIN = 0 V, VCC = 3.6 V or 0 V -10 ±0.05 10 SERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC) f = 40 MHz 40 50 ICCD Serializer supply current, worst case RL = 27 Ω, See Figure 2 mA f = 10 MHz 20 25 ICCXD Serializer supply current, power down PWRDN = 0.8 V 200 500 µA DESERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC) f = 40 MHz 63 75 ICCR Deserializer supply current, worst case CL = 15 pF, See Figure 3 mA f = 10 MHz 15 35 ICCXR Deserializer supply current, power down PWRDN = 0.8 V, REN = 0.8 V 0.36 1 mA over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tTCP Transmit clock period 25 T 100 ns tTCIH Transmit clock high time 0.4T 0.5T 0.6T ns tTCIL Transmit clock low time 0.4T 0.5T 0.6T ns tt(CLK) TCLK input transition time See Figure 6 3 6 ns tJIT TCLK input jitter 150 ps (RMS) 8 |
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