SA8028 datasheet(11/28 Pages) PHILIPS

Part #	SA8028

Description	2.5 GHz sigma delta fractional-N / 760 MHz IF integer frequency synthesizers

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Manufacturer	PHILIPS [NXP Semiconductors]

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Philips Semiconductors

Product data

SA8028

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

2002 Feb 22

11

2.0

SERIAL PROGRAMMING BUS

A simple 3-line bidirectional serial bus is used to program the circuit.

The 3 lines are DATA, CLOCK and STROBE. When the STROBE = 0,

the clock driver is enabled and on the positive edges of the CLOCK

signal, DATA is clocked into temporary shift registers. When the

STROBE = 1, the clock is disabled and the data in the shift register

is latched into different working registers, depending on the address

bits. In order to fully program the circuit, 3 words must be sent in the

following order: C, B, and A. An additional word, the D-word, is for

test purposes only: all bits in this test word should be initialized to 0

for normal operation. The N value of the B-word is stored temporarily

until the A-word is loaded to avoid temporarily false N settings, while

the corresponding fractional ratio Kn is not yet active. When a new

fractional ratio is loaded through the A-word, the fractional sigma

delta modulator is not reset, i.e., it will start the new fractional

sequence from the last state of the previously executed sequence. A

typical programming sequence is illustrated in Figure 10.

When loading several words in series, the minimum STROBE high

time between words must be observed (refer to Figure 8).

Unlike the earlier SA80xx family members, SA8028 has the built-in

feature to output the contents of an addressable internal register.

For the current SA8028, only the momentary division ratio N (RF

divider) can be retrieved through the serial bus. The handshake

protocol requires a “request to read” to be sent prior to each “read”,

i.e., by sending a D-word with the TreadN-bit (<D11>) set to “high”.

Immediately after the transition of “STROBE” from low-to-high,

four (4) clock pulses are needed to prepare the data for output and

another nine (9) clock pulses are needed to accomplish the serial

reading with LSB first. A high-to-low transition of “STROBE” then

resets the serial bus to the input mode. The timing diagram is

presented in Figure 9. In general, a high-to-low transition of the

“STROBE” signal will instantaneously reset the serial bus to the

input mode, even when the chip is in the output mode.

Table 2. Serial bus timing requirements (see Figures 8 and 9)

VDD = VDDCP =+3.0 V; Tamb = +25 °C unless otherwise specified. (Guaranteed by design.)

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Serial programming clock; CLK

tr

Input rise time

–

10

40

ns

tf

Input fall time

–

10

40

ns

Tcy

Clock period

100

–

ns

Enable programming; STROBE

tSTART, tSTART;R

Delay to rising clock edge

40

–

ns

tW

Minimum inactive pulse width

1/fCOMP

–

ns

tSU;E

Enable set-up time to next clock edge

20

–

ns

tRESET

Reset data line to input mode

20

–

ns

Register serial input data; DATA (I)

tSU;DAT

Input data to clock set-up time

20

–

ns

tHD;DAT

Input data to clock hold time

20

–

ns

Register serial output data; DATA (O)

tSU;DAT;R

Input clock to data set-up time

20

–

ns

SR02296

CLK

DATA

STROBE

LSB

ADDRESS

tSU;DAT

tW

TCY

tSTART

tf

tr

MSB

tSU;E

tHD;DAT

>=0

Figure 8.

Serial bus “Write” timing diagram.

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