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SN65HVD231QDRQ1 Datasheet(PDF) 8 Page - Texas Instruments |
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SN65HVD231QDRQ1 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 32 page SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 8 www.ti.com driver switching characteristics at TA = 25°C (unless otherwise noted) SN65HVD232Q PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output 35 85 ns tPHL Propagation delay time, high-to-low-level output 70 120 ns tsk(p) Pulse skew (|tP(HL) − tP(LH)|) CL = 50 pF, See Figure 4 35 ns tr Differential output signal rise time CL 50 pF, See Figure 4 25 50 100 ns tf Differential output signal fall time 40 55 80 ns receiver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIT+ Positive-going input threshold voltage See Table 1 750 900 mV VIT− Negative-going input threshold voltage See Table 1 500 650 mV Vhys Hysteresis voltage (VIT+ − VIT−) 100 mV VOH High-level output voltage − 6 V ≤ VID ≤ 500 mV, IO = −8 mA, See Figure 5 2.4 V VOL Low-level output voltage 900 mV ≤ VID ≤ 6 V, IO = 8 mA, See Figure 5 0.4 V VIH = 7 V 100 250 A I VIH = 7 V, VCC = 0 V Other input at 0 V, 100 350 µA II Bus input current VIH = −2 V Other input at 0 V, D = 3 V − 200 −30 A VIH = −2 V, VCC = 0 V − 100 −20 µA Ci CANH, CANL input capacitance Pin-to-ground, VI = 0.4 sin(4E6πt) + 0.5 V V(D) = 3 V, 32 pF Cdiff Differential input capacitance Pin-to-pin, VI = 0.4 sin(4E6πt) + 0.5 V V(D) = 3 V, 16 pF Rdiff Differential input resistance Pin-to-pin, V(D) = 3 V 40 70 100 k Ω RT CANH, CANL input resistance 20 35 50 k Ω ICC Supply current See driver † All typical values are at 25 °C and with a 3.3-V supply. receiver switching characteristics at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output 35 50 ns tPHL Propagation delay time, high-to-low-level output See Figure 6 35 50 ns tsk(p) Pulse skew (|tP(HL) − tP(LH)|) See Figure 6 10 ns tr Output signal rise time See Figure 6 1.5 ns tf Output signal fall time See Figure 6 1.5 ns t(loop) Total loop delay, driver input to receiver output V(RS) = 0 V 70 135 t(loop) Total loop delay, driver input to receiver output RS with 10 kΩ to ground 105 175 ns t(loop) Total loop delay, driver input to receiver output RS with 100 kΩ to ground 535 920 |
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