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SN65HVD101RGBR Datasheet(PDF) 4 Page - Texas Instruments

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Part # SN65HVD101RGBR
Description  IO-Link PHY for Device Nodes
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN65HVD101RGBR Datasheet(HTML) 4 Page - Texas Instruments

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SN65HVD101, SN65HVD102
SLLSE84B – MAY 2011 – REVISED APRIL 2015
www.ti.com
Pin Functions (continued)
PIN
DESCRIPTION
NAME
NUMBER
TYPE(1)
GND
3, 6, 13
P
Logic ground potential
Special Connect Pins
Connect this pin to ground to make Vcc OUT = 3.3V. Leave this pin floating to make Vcc OUT =
VCC SET
1
I
5V.
Input for current limit adjustment. Connect resistor RSET between this pin and ground. For RSET
ILIMADJ
4
A
values see Figure 2.
Power-Good indicator. Connect this pin via pull-up resistor to Vcc OUT. A HIGH at this pin indicates
PWR_OK
5
OD
that L+ and Vcc OUT are at correct levels.
Temperature-Good indicator. Connect this pin via pull-up resistor to Vcc OUT. High-impedance at
Temp_OK
19
OD
this pin indicates that the internal temperature is at a safe level. A low at this pin indicates the
device is approaching thermal shutdown.
NC
2, 9, 11
No Connection. Leave these pins floating (open)
In normal operation, the PHY sets the output state of the CQ pin when the driver is enabled. During fault
conditions, the driver may be disabled by internal circuits.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Steady state
–40
40(2) (3)
V
Line voltage
L+, CQ
Transient pulse width <100 µs
–50
50
V
Voltage difference
|VL+ – VCQ|
40
Supply voltage
VCC
–0.3
6
V
Input voltage
TX, EN, VCC_SET, ILIMADJ,
–0.3
6
V
Output voltage
RX, CUR_OK, WAKE, PWR_OK
–0.3
6
V
Output current
RX, CUR_OK, WAKE, PWR_OK
–5
5
mA
Storage temperature, Tstg
–65
150
°C
Junction temperature, TJ
180
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltages are with reference to the GND pin, unless otherwise specified.
(3)
GND pin and L– line should be at the same DC potential
7.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM, all pins), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
4
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Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: SN65HVD101 SN65HVD102


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