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PC87391 Datasheet(PDF) 69 Page - National Semiconductor (TI) |
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PC87391 Datasheet(HTML) 69 Page - National Semiconductor (TI) |
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69 / 148 page  2.0 Device Architecture and Configuration (Continued) 69 www.national.com 2.19.8 X-Bus Memory Configuration Register This register is reset by hardware to 00h. Location: Index F4h Type: R/W 2.19.9 X-Bus Memory Base Address High Byte Register This register describes the high byte for the user-defined memory zone mapped to the X-Bus (decoded as bits 31 to 24 of the 32-bit address range, bits 15-0 are 0). This register is reset by hardware to 00h. Location: Index F5h Type: R/W Bit 76543210 Name BIOS FWH ID BIOS FWH Enable User- Defined Memory Space Enable BIOS Extended Space Enable BIOS LPC Enable Reset 0000 Depends on strap setting. Bit Description 7-4 BIOS FWH ID. The identification nibble that is part of a FWH transaction (see Section 2.8.1 for details), which identifies the device addressed. 3 BIOS FWH Enable. When set, enables PC8739x response to LPC-FWH transactions to the BIOS-FWH space, if the BIOS FWH ID matches the ID of the transaction.. The reset value of this register is defined by the XCNF2- 0 configuration inputs. The value of this bit is later updated, based on the detected host BIOS scheme, see Section 2.19.3 for details. 0: Disabled (default when XCNF disable BIOS configuration) 1: Enabled (default when XCNF enable BIOS configuration) 2 User-Defined Memory Space Enable. When set, enables the PC8739x to respond to LPC memory read and write accesses in the user-defined memory area range. The base address and size of the user-defined range is specified by X-Bus Memory Base Address High and Low Byte registers and the X-Bus Memory Size Configuration register. 0: Disabled (default) 1: Enabled 1 BIOS Extended Space Enable. Expands the BIOS address space to which the PC8739x responds to include the Extended BIOS address range. 0: Disabled (default) 1: Enabled 0 BIOS LPC Enable. Enables the PC8739x to respond to LPC memory accesses to the BIOS-LPC space. The reset value of this register is defined by the XCNF2-0 configuration inputs. The value of this bit is later updated, based on the detected host BIOS scheme (see Section 2.19.3 for details). 0: Disabled (default when XCNF disable BIOS configuration) 1: Enabled (default when XCNF enable BIOS configuration) Bit 76543210 Name User-Defined Memory Zone Address High Reset 00000000 Bit Description 7-0 User-Defined Memory Zone Address High. Defines the higher 8 bits of the user-defined memory block base address. The base address should be aligned on the selected block size. |
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