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PC87391 Datasheet(PDF) 34 Page - National Semiconductor (TI) |
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PC87391 Datasheet(HTML) 34 Page - National Semiconductor (TI) |
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34 / 148 page  2.0 Device Architecture and Configuration (Continued) 34 www.national.com 2.4 INTERRUPT SERIALIZER The Interrupt Serializer translates parallel interrupt request (PIRQ) signals received from external devices, via the PIRQn (n can be A, B, C or D) pins and from internal IRQ sources, into serial interrupt request data transmitted over the SERIRQ bus. This enables the integration of devices that support only parallel IRQs in a system which supports only serial IRQs. PIRQ signals that enter the device or internal IRQs are fed into an IRQ Mapping, Enable, and Polarity Control block. This block maps them to their associated IRQ slots. The IRQs are then fed into the Interrupt Serializer, where they are translated into serial data and transmitted over the SERIRQ bus. The PIRQn input value is routed to the Interrupt Serializer as the IRQ value to be driven onto IRQ slot n. The same slot cannot be shared among different interrupt sources in this device. When a transition is sensed on an IRQ source,the new value of the IRQ source is transmitted over the SERIRQ bus during the corresponding IRQ slot. For example, when a transition on PIRQA is sensed, the new value of PIRQA is transmitted during slot n of the SERIRQ bus. Figure 4 shows the mechanism for both interrupt serialization and wake-up. Figure 4. Interrupt Serialization and Wake-Up Mechanism 2.5 WAKE-UP CONTROL The Wake-Up Control module receives the parallel interrupt request (PIRQn) signals from external devices and the IRQ sig- nals from internal sources. It generates the PWUREQ system wake-up signal. All mapped IRQ signals, both internal and external, enter the Wake-Up Enable Control block. If one of them becomes active and is enabled for wake-up, an active PWUREQ signal is generated. 2.6 THE PARALLEL PORT MULTIPLEXER (PPM) The Parallel Port Multiplexer (PPM) allows connection of an external Floppy Disk Drive (FDD) through the Parallel Port con- nector (25-pin DIN) instead of, or in addition to, the internal FDD on the normal FDC header. This is done by turning the Parallel Port pins into an additional set of FDC pins, while isolating them from Parallel Port functionality (see Section 1.4 for a signal multiplexing description). A printer, or any other parallel device, may be exchanged with an external FDD without turning the system off. The PPM logic automatically detects whether a parallel device or the FDD is connected, and routes the Parallel Port pins to either the Parallel Port or the FDC functional blocks accordingly. See Figure 5. To enable PPM mode, set bits 6-5 (Pin 35 Function Select) of the SIOCF5 register to the values that represent the desired configuration (see Section 2.10.6). The control of the connection, after enabling PPM mode, is done by bit SIOCF5[7] (PNF status) of this register as follows: q PNF status = 1, PPM is inactive and the Parallel Port pins are assigned Parallel Port functionality q PNF status = 0, PPM is active and the Parallel Port pins are assigned FDC functionality. The value of bit SIOCF5[7] is determine by the PNF pin signal and the PNF polarity setting (bits SIOCF5[6:5]). When PPM mode is disabled (both bits 6-5 of the SIOCF5 register = 0), the Parallel Port pins are assigned Parallel Port functionality, regardless of the value of PNF. The internal FDD on the normal FDC pins, and the external FDD on the Parallel Port pins can be assigned as Drive A and Drive B, respectively, or the drive assignment can be switched between them. IRQ Mapping and Polarity Control Internal IRQ Sources Control Signals PIRQn Interrupt Serializer Bus Interface SERIRQ IRQ1 IRQ15 PWUREQ Wake-Up Enable Control Pins |
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