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DP83932CVF-33 Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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DP83932CVF-33 Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 98 page  10 Functional Description (Continued) 14 FIFO AND CONTROL LOGIC The SONIC incorporates two independent 32-byte FIFOs for transferring data tofrom the system interface and from to the network The FIFOs providing temporary storage of data free the host system from the real-time demands on the network The way in which the FIFOS are emptied and filled is con- trolled by the FIFO threshold values and the Block Mode Select bits (BMS Section 432) The threshold values de- termine how full or empty the FIFOs can be before the SONIC will request the bus to get more data from memory or buffer more data to memory When block mode is set the number of bytes transferred is set by the threshold value For example if the threshold for the receive FIFO is 4 words then the SONIC will always transfer 4 words from the receive FIFO to memory If emptyfill mode is set however the number of bytes transferred is the number required to fill the transmit FIFO or empty the receive FIFO More specific information about how the threshold affects reception and transmission of packets is discussed in Sections 141 and 142 below 141 Receive FIFO To accommodate the different transfer rates the receive FIFO (Figure 1-5 ) serves as a buffer between the 8-bit net- work (deserializer) interface and the 1632-bit system inter- face The FIFO is arranged as a 4-byte wide by 8 deep memory array (8 long words or 32 bytes) controlled by three sections of logic During reception the Byte Ordering logic directs the byte stream from the deserializer into the FIFO using one of four write pointers Depending on the selected byte-ordering mode data is written either least sig- nificant byte first or most significant byte first to accommo- date little or big endian byte-ordering formats respectively As data enters the FIFO the Threshold Logic monitors the number of bytes written in from the deserializer The pro- grammable threshold (RFT10 in the Data Configuration Register) determines the number of words (or long words) written into the FIFO from the MAC unit before a DMA re- quest for system memory occurs When the threshold is reached the Threshold Logic enables the Buffer Manage- ment Engine to read a programmed number of 16- or 32-bit words (depending upon the selected data width) from the FIFO and transfers them to the system interface (the sys- tem memory) using DMA The threshold is reached when the number of bytes in the receive FIFO is greater than the value of the threshold For example if the threshold is 4 words (8 bytes) then the Threshold Logic will not cause the Buffer Management Engine to write to memory until there are more than 8 bytes in the FIFO The Buffer Management Engine reads either the upper or lower half (16 bits) of the FIFO in 16-bit mode or reads the complete long word (32 bits) in 32-bit mode If after the transfer is complete the number of bytes in the FIFO is less then the threshold then the SONIC is done This is always the case when the SONIC is in emptyfill mode If however for some reason (eg latency on the bus) the number of bytes in the FIFO is still greater than the threshold value the Threshold Logic will cause the Buffer Management En- gine to do a DMA request to write to memory again This later case is usually only possible when the SONIC is in block mode When in block mode each time the SONIC requests the bus only a number of bytes equal to the threshold value will be transferred The Threshold Logic continues to monitor the number of bytes written in from the deserializer and en- ables the Buffer Management Engine every time the thresh- old has been reached This process continues until the end of the packet Once the end of the packet has been reached the serializer will fill out the last word (16-bit mode) or long word (32-bit mode) if the last byte did not end on a word or long word boundary respectively The fill byte will be 0FFh Immediate- ly after the last byte (or fill byte) in the FIFO the received packets status will be written into the FIFO The entire pack- et including any fill bytes and the received packet status will be buffered to memory When a packet is buffered to mem- ory by the Buffer Management Engine it is always taken from the FIFO in words or long words and buffered to mem- ory on word (16-bit mode) or long word (32-bit mode) boundaries Data from a packet cannot be buffered on odd byte boundaries for 16-bit mode and odd word boundaries for 32-bit mode (see Section 33) For more information on the receive packet buffering process see Section 34 142 Transmit FIFO Similar to the Receive FIFO the Transmit FIFO (Figure 1-6 ) serves as a buffer between the 1632-bit system interface and the network (serializer) interface The Transmit FIFO is also arranged as a 4 byte by 8 deep memory array (8 long words or 32 bytes) controlled by three sections of logic Before transmission can begin the Buffer Management En- gine fetches a programmed number of 16- or 32-bit words from memory and transfers them to the FIFO The Buffer Management Engine writes either the upper or lower half (16 bits) into the FIFO for 16-bit mode or writes the com- plete long word (32 bits) during 32-bit mode The Threshold logic monitors the number of bytes as they are written into the FIFO When the threshold has been reached the Transmit Byte Ordering state machine begins reading bytes from the FIFO to produce a continuous byte stream for the serializer The threshold is met when the number of bytes in the FIFO is greater than the value of the threshold For example if the transmit threshold is 4 words (8 bytes) the Transmit Byte Ordering state machine will not begin reading bytes from the FIFO until there are 9 or more bytes in the buffer The Buffer Management Engine contin- ues replenishing the FIFO until the end of the packet It does this by making multiple DMA requests to the system interface Whenever the number of bytes in the FIFO is equal to or less than the threshold value the Buffer Man- agement Engine will do a DMA request If block mode is set then after each request has been granted by the system the Buffer Management Engine will transfer a number of bytes equal to the threshold value into the FIFO If emptyfill mode is set the FIFO will be completely filled in one DMA request Since data may be organized in big or little endian byte or- dering format the Transmit Byte Ordering state machine uses one of four read pointers to locate the proper byte within the 4 byte wide FIFO It also determines the valid number of bytes in the FIFO For packets which begin or end at odd bytes in the FIFO the Buffer Management En- gine writes extraneous bytes into the FIFO The Transmit Byte Ordering state machine detects these bytes and only transfers the valid bytes to the serializer The Buffer Man- agement Engine can read data from memory on any byte boundary (see Section 33) See Section 35 for more infor- mation on transmit buffering 8 |
Similar Part No. - DP83932CVF-33 |
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Similar Description - DP83932CVF-33 |
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