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CY8C3245LTI-163 Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY8C3245LTI-163
Description  Programmable System-on-Chip (PSoC짰)
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C3245LTI-163 Datasheet(HTML) 7 Page - Cypress Semiconductor

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PSoC® 3: CY8C32 Family Data Sheet
Document Number: 001-56955 Rev. *Y
Page 7 of 128
Figure 2-3. 48-pin SSOP Part Pinout
Figure 2-4. 48-pin QFN Part Pinout[6]
SSOP
VSSA
(SIO) P12[3]
247
VCCA
(GPIO) P0[0]
346
P15[3] (GPIO, KHZ XTAL: XI)
(GPIO) P0[1]
445
P12[0] (SIO, I2C1: SCL)
VDDIO0
742
P12[1] (SIO, I2C1: SDA)
643
(EXTREF0, GPIO) P0[3]
P15[1] (GPIO, MHZ XTAL: XI)
(GPIO) P0[5]
940
P15[0] (GPIO, MHZ XTAL: XO)
(IDAC0, GPIO) P0[6]
10
39
VCCD
(GPIO) P0[7]
11
38
VSSD
VCCD
12
37
VDDD
VSSD
13
36
P15[7] (USBIO, D-, SWDCK)
VDDD
14
35
P15[6] (USBIO, D+, SWDIO)
(GPIO) P2[3]
15
34
P1[7] (GPIO)
(GPIO) P2[4]
16
33
P1[6] (GPIO)
VDDIO2
17
32
VDDIO1
(GPIO) P2[5]
18
31
P1[5] (GPIO, NTRST)
(GPIO) P2[6]
19
30
P1[4] (GPIO, TDI)
(GPIO) P2[7]
20
29
P1[3] (GPIO, TDO, SWV)
VSSB
21
28
IND
22
27
P1[1] (GPIO, TCK, SWDCK)
VBOOST
23
26
P1[0] (GPIO, TMS, SWDIO)
VBAT
24
25
VDDA
(SIO) P12[2]
148
VDDIO3
(GPIO) P0[4]
841
P15[2] (GPIO, KHZ XTAL: XO)
(GPIO) P0[2]
544
Lines show
VDDIO to I/O
supply
association
P1[2] (GPIO, CONFIGURABLE XRES)
[5]
[5]
Notes
5. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
6. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal. For more information, see AN72845, Design Guidelines for QFN Devices.
QFN
( TOP VIEW)
10
11
12
VSSB
IND
VBOOST
VBAT
35
34
33
32
31
30
29
28
27
26
25
36
1
2
3
4
5
6
7
8
9
VCCA
VSSA
VDDA
P12[2] (SIO)
P12[3] (SIO)
P0[0] (GPIO)
P0[1] (GPIO)
P0[2] (GPIO)
P0[3] (EXTREF0, GPIO)
(GPIO) P2[6]
(GPIO) P2[7]
(GPIO, NTRST) P1[5]
(GPIO, TDI) P1[4]
(GPIO, TDO, SWV) P1[3]
(GPIO, TCK, SWDCK) P1[1]
(GPIO, TMS, SWDIO) P1[0]
(GPIO, Configurable XRES) P1[2]
P12[1] (SIO, I2C1: SDA)
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
Lines show
VDDIO to I/O
supply
association


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