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SN74HC32PWLE Datasheet(PDF) 10 Page - Texas Instruments

Part # SN74HC32PWLE
Description  Quadruple 2-Input Positive-OR Gates
Download  30 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN74HC32PWLE Datasheet(HTML) 10 Page - Texas Instruments

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VCC
Input 1
0.1 PF
Input 2
Input 3
Input 4
Output 1
Output 2
Output 3
Output 4
Enable
Copyright © 2016, Texas Instruments Incorporated
10
SN54HC32, SN74HC32
SCLS200E – DECEMBER 1982 – REVISED JULY 2016
www.ti.com
Product Folder Links: SN54HC32 SN74HC32
Submit Documentation Feedback
Copyright © 1982–2016, Texas Instruments Incorporated
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SNx4HC32 is an extremely versatile device with far more available applications than could be listed here.
The application chosen as an example is using all four OR gates in a single package to provide a four channel
output enable from a single active low enable signal (Enable). This circuit outputs a logic HIGH on all channels
when disabled (Enable is HIGH), and passes the input signals when enabled (Enable is LOW).
9.2 Typical Application
Using a quad OR gate as a 4-channel active low enable with high output off state.
Figure 6. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads, so
routing and load conditions must be considered to prevent ringing.
The minimum output pulse time is approximately three times tpd from Switching Characteristics for the selected
VCC, device, and temperature range.
9.2.2 Detailed Design Procedure
Logic
All four input channels are to be enabled or disabled simultaneously
The enable signal is active low (LOW = enabled, HIGH = disabled)
All four outputs are to output logic HIGH while disabled
Inputs
Each input must follow requirements specified in Absolute Maximum Ratings:
Avoid exceeding input voltages


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