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DP83934VF Datasheet(PDF) 57 Page - National Semiconductor (TI) |
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DP83934VF Datasheet(HTML) 57 Page - National Semiconductor (TI) |
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57 / 104 page  70 Bus Interface (Continued) 731 Acquiring The Bus The SONIC-T requests the bus when 1) its FIFO threshold has been reached or 2) when the descriptor areas in memo- ry (ie RRA RDA CDA and TDA) are accessed Note that when the SONIC-T moves from one area in memory to an- other (eg RBA to RDA) it always deasserts its bus request and then requests the bus again when accessing the next area in memory The SONIC-T provides two methods to acquire the bus for compatibility with NationalIntel or Motorola type microproc- essors These two methods are selected by setting the proper level on the BMODE pin Figures 7-3 and 7-4 show the NationalIntel (BMODE e 0) and Motorola (BMODE e 1) bus request timing Descrip- tions of each mode follows For both modes when the SONIC-T relinquishes the bus there is an extra holding state (Th) for one bus cycle after the last DMA cycle (T2) This assures that the SONIC-T does not contend with an- other bus master after it has released the bus BMODE e 0 The NationalIntel processors require a 2-way handshake using a HOLD REQUESTHOLD ACKNOWLEDGE protocol (Figure 7-3) When the SONIC-T needs to access the bus it issues a HOLD REQUEST (HOLD) to the microprocessor The microprocessor responds with a HOLD ACKNOWL- EDGE (HLDA) to the SONIC-T The SONIC-T then begins its memory transfers on the bus As long as the CPU main- tains HLDA active the SONIC-T continues until it has fin- ished its memory block transfer The CPU however can preempt the SONIC-T from finishing the block transfer by deasserting HLDA before the SONIC-T deasserts HOLD This allows a higher priority device to preempt the SONIC-T from continuing to use the bus The SONIC-T will request the bus again later to complete any operation that it was doing at the time of preemption The HLDA signal is sam- pled synchronously by the SONIC-T at the rising edge of the BSCK setup time must be met to ensure proper operation As shown in Figure 7-3 the SONIC-T will assert HOLD to either the falling or rising edge of the bus clock (BSCK) The default is for HOLD to be asserted on the falling edge Set- ting the PH bit in the DCR2 (see Section 637) causes HOLD to be asserted bus clock later on the rising edge (shown by the dotted line) Before HOLD is asserted the SONIC-T checks the HLDA line If HLDA is asserted HOLD will not be asserted until after HLDA has been deasserted first Note If HLDA is driven low to preempt the SONIC-T from the bus while the SONIC-T is accessing the CAM (LCAM command) the SONIC-T will get off the bus but will not deassert HOLD even though the status bit will indicate idle state If HLDA is driven low while the SONIC-T is accessing descriptor areas (RRA RDA TDA) the SONIC-T will be preempted normally (ie get off the bus and deassert HOLD) and the HOLD signal will be reasserted again after one bus clock If HLDA is driven low while the SONIC-T is accessing data areas (RBA TBA) the SONIC-T will be preempted normally but may not reassert HOLD unless required to do so depending on the threshold condition of the FIFO BMODE e 1 The Motorola protocol requires a 3-way handshake using a BUS REQUEST BUS GRANT and BUS GRANT AC- KNOWLEDGE handshake (Figure 7-4) When using this pro- tocol the SONIC-T requests the bus by lowering BUS RE- QUEST BR The CPU responds by issuing BUS GRANT BG Upon receiving BG the SONIC-T assures that all devices have relinquished control of the bus before using the bus The following signals must be deasserted before the SON- IC-T acquires the bus BGACK AS DSACK01 STERM (Asynchronous Mode Only) Deasserting BGACK indicates that the previous master has released the bus Deasserting AS indicates that the previ- ous master has completed its cycle and deasserting DSACK01 and STERM indicates that the previous slave has terminated its connection to the previous master The SONIC-T maintains its mastership of the bus until it deas- serts BGACK It can not be preempted from the bus TLF11719 – 30 FIGURE 7-3 Bus Request Timing (BMODE e 0) 57 |
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