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DP83934VF Datasheet(PDF) 41 Page - National Semiconductor (TI) |
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DP83934VF Datasheet(HTML) 41 Page - National Semiconductor (TI) |
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41 / 104 page  60 SONIC-T Registers (Continued) 632 Data Configuration Register (Continued) Bit Description 10 SBUS SYNCHRONOUS BUS MODE The SBUS bit is used to select the mode of system bus operation when SONIC-T is a bus master This bit selects the internal ready line to be either a synchronous or asynchronous input to SONIC-T during block transfer DMA operations 0 Asynchronous mode RDYi (BMODE e 0) or DSACK01 (BMODE e 1) are respectively internally synchronized at the falling edge of the bus clock (T2 of the DMA cycle) No setup or hold times need to be met with kS2–S5l respect to this edge to guarantee proper bus operation The minimum memory cycle time is 3 bus clocks 1 Synchronous mode RDYi (BMODE e 0) and DSACK01 (BMODE e 1) must respectively meet the setup and kS2–S5l hold times with respect to the rising edge of T1 or T2 to guarantee proper bus operation 9 8 USR10 USER DEFINABLE PINS The USR10 bits report the level of the USR10 signal pins respectively after a chip hardware reset If the USR10 signal pins are at a logical 1 (tied to VCC) during a hardware reset the USR10 bits are set to a 1 If the USR10 pins are at a logical 0 (tied to ground) during a hardware reset the USR10 bits are set to a 0 These bits are latched on the rising edge of RST Once set they remain setreset until the next hardware reset 7 6 WC10 WAIT STATE CONTROL These encoded bits determine the number of additional bus cycles (T2 states) that are added during each DMA cycle WC1 WC0 Bus Cycles Added 00 0 01 1 10 2 11 3 5 DW DATA WIDTH SELECT These bits select the data path width for DMA operations DW Data Width 0 16-bit 1 32-bit 4 BMS BLOCK MODE SELECT FOR DMA Determines how data is emptied or filled into the Receive or Transmit FIFO 0 Emptyfill mode All DMA transfers continue until either the Receive FIFO has emptied or the Transmit FIFO has filled completely 1 Block mode All DMA transfers continue until the programmed number of bytes RFT0 (RFT1 during reception or TF0 TF1 during transmission) have been transferred (See note for TFT0 TFT1) 3 2 RFT1RFT0 RECEIVE FIFO THRESHOLD These encoded bits determine the number of words (or long words) that are written into the receive FIFO from the MAC unit before a receive DMA request occurs (See Section 35) LB1 LB0 Function 0 0 2 words or 1 long word (4 bytes) 0 1 4 words or 2 long words (8 bytes) 1 0 8 words or 4 long words (16 bytes) 1 1 12 words or 6 long words (24 bytes) Note In block mode (BMS bit e 1) the receive FIFO threshold sets the number of words (or long words) written to memory during a receive DMA block cycle 1 0 TFT1TFT0 TRANSMIT FIFO THRESHOLD These encoded bits determine the minimum number of words (or long words) the DMA section maintains in the transmit FIFO A bus request occurs when the number of words drops below the transmit FIFO threshold (See Section 35) LB1 LB0 Function 0 0 4 words or 2 long words (8 bytes) 0 1 18 words or 4 long words (16 bytes) 1 0 12 words or 6 long words (24 bytes) 1 1 14 words or 7 long words (28 bytes) Note In block mode (BMS e 1) the number of bytes the SONIC-T reads in a single DMA burst equals the transmit FIFO threshold value If the number of words or long words needed to fill the FIFO is less than the threshold value then only the number of reads required to fill the FIFO in a single DMA burst will be made Typically with the FIFO threshold value set to 12 or 14 words the number of memory reads needed is less than the FIFO threshold value 41 |
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