Electronic Components Datasheet Search |
|
SLK2501IPZPG4 Datasheet(PDF) 10 Page - Texas Instruments |
|
SLK2501IPZPG4 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 22 page www.ti.com Frame Synchronization Testability IDDQ Function Local Loopback SLK2501 SLLS502C – OCTOBER 2001 – REVISED MARCH 2007 The SLK2501 has a SONET/SDH-compatible frame detection circuit that can be enabled or disabled by the user. Frame detection is enabled when the FRAMEN pin is high. When enabled it detects the A1, A2 framing pattern, which is used to locate and align the byte and frame boundaries of the incoming data stream. When FRAMEN is low the frame detection circuitry is disabled and the byte boundary is frozen to the location found when detection was previously enabled. The frame detect circuit searches the incoming data for three consecutive A1 bytes followed immediately by one A2 byte. The data alignment circuit then aligns the parallel output data to the byte and frame boundaries of the incoming data stream. During the framing process the parallel data bus will not contain valid and aligned data. Upon detecting the third A1, A2 framing patterns that are separated by 125 µs from each other, the FSYNC signal goes high for four RXCLK cycles, indicating frame synchronization has been achieved. The probability that random data in a SONET/SDH data stream will mimic the framing pattern in the data payload is extremely low. However, there is a state machine built in to prevent false reframing if a framing pattern does show up in the data payload. bility The SLK2501 has a comprehensive suite of built-in self-tests. The Loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. The enable pin allows for all circuitry to be disabled so that an Iddq test can be performed. The PRBS function allows for a BIST (built-in self-test). When held low, the ENABLE pin disables all quiescent power in both the analog and digital circuitry. This allows for IDDQ testing on all power supplies and can also be used to conserve power when the link is inactive. The LLOOP signal pin controls the local loopback. When LLOOP is high, the loopback mode is activated and the parallel transmit data is selected and presented on the parallel receive data output pins. The parallel transmit data is also multiplexed and presented on the high-speed serial transmit pins. Local Loopback can only be enabled when the device is under transceiver mode. Figure 4. Local Loopback Data Path 10 Submit Documentation Feedback |
Similar Part No. - SLK2501IPZPG4 |
|
Similar Description - SLK2501IPZPG4 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |