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TMS370C310ANT Datasheet(PDF) 8 Page - Texas Instruments |
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TMS370C310ANT Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 52 page  TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F -- MAY 1987 -- REVISED FEBRUARY 1997 8 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443 TMS370Cx1x CPU (continued) 256-Byte RAM (Register File/Stack) 128-Byte RAM (Register File/Stack) Reserved† Peripheral File Reserved† 256-Byte Data EEPROM Not Available‡ 7FC0h Trap 15--0 7FE0h Reserved 7FF4h Interrupt 3 Interrupt 2 Interrupt 1 Reset 1010h 1020h System Control Digital Port Control 1030h 1040h Timer 1 Peripheral Control Vectors 7FDFh 7FF3h 7FF5h 101Fh 102Fh 103Fh 104Fh -- -- -- -- -- -- -- Not Available‡ SPI Control Timer 1 Serial Peripheral Interface 7FFAh 7FFBh -- 7FFCh 7FFDh -- 7FFEh 7FFFh -- 0000h 0080h 007Fh 1010h 104Fh 1050h 1EFFh 1F00h 1FFFh 2000h 5FFFh 6000h 6FFFh 7000h 77FFh 7800h FFFFh 100Fh 8K Bytes Start at 6000h 4K Bytes Start at 7000h 2K Bytes Start at 7800h Interrupts and Reset Vectors; Trap Vectors 7FBFh 7FC0h 7FFFh 8000h 7FF6h 7FF7h ---- 7FF8h 7FF9h -- Peripheral File Control Registers 0100h 00FFh † Reserved means that the address space is reserved for future expansion. ‡ Not available means that the address space is not accessible. Figure 3. TMS370Cx1x Memory Map RAM/register file (RF) Locations within the RAM address space can serve as the RF, general-purpose read/write memory, program memory, or the stack instructions. The TMS370Cx10, TMS370Cx11, and TMS370C312 contain 128 bytes of internal RAM mapped beginning at location 0000h (R0) and continuing through location 007Fh (R127) which is shown in Table 4 along with ’712 devices. Table 4. RAM Memory Map ’x10, ’x11 AND ’312 ’712 RAM size 128 bytes 256 bytes Memory mapped 0000h--007Fh 0000h--00FFh The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the stack pointer is contained in register B. Registers A and B are the only registers cleared on reset. |
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