SCAN926260

SNLS153H – JUNE 2002 – REVISED APRIL 2013

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Functional Description

The SCAN926260 combines six 1:10 deserializers into a single chip. Each of the six deserializers accepts a Bus

LVDS data stream from TI's DS92LV1021, DS92LV1023, DS92LV8028, SCAN921023, or SCAN921025

Serializer. The deserializers then recover the clock and data to deliver the resulting 10-bit wide words to the

outputs.

Each of the six channels acts completely independent of each other. Each independent channel has outputs for

a 10-bit wide data word, a recovered clock output, and a lock-detect output.

The SCAN926260 has three operating states: Initialization, Data Transfer, and Resynchronization. In addition,

there are two passive states: Powerdown and Tri-state. During normal operation, the SCAN6260 also has the

capability of utilizing the IEEE 1149.1 test modes (JTAG) or the Built-In Self Test mode (BIST).

The following sections describe each operating mode, passive states, and the JTAG and BIST modes.

Initialization

Before the SCAN926260 receives and deserializes data, it and the transmitting Serializer must initialize the link.

Initialization refers to synchronizing the Serializer's and the Deserializer's PLL's to local clocks. The local clocks

must be within ±5% of the incoming transmitter clock frequency. After all devices synchronize to local clocks, the

Deserializer synchronizes to the Serializer as the second and final initialization step.

Step 1: After applying power to the Deserializer, the outputs are held high and the on-chip Power-on Reset

locking to the local clock (REFCLK). A local on-board oscillator or other source that provides the specified clock

input to the REFCLK pin.

Step 2: The Deserializer PLL must synchronize to the Serializer to complete the initialization. Refer to the

Serializer data sheet for proper operation during the Initialization State. The Deserializer identifies the rising clock

edge in a synchronization pattern or pseudo-random data and after 80 clock cycles will synchronize to the data

stream from the Serializer. At the point where the Deserializer's PLL locks to the embedded clock, the LOCKn

pin goes low and valid data appears at the outputs.

Data Transfer

After initialization, the Serializer transfers data to the Deserializer. The serial data stream includes a start and

stop bit appended by the serializer, which frames the ten data bits. The start bit is always high and the stop bit is

always low. The start and stop bits also function as clock bits embedded in the serial stream.

The Serializer transmits the data and clock bits (10+2 bits) at 12 times the TCLK frequency. For example, if

TCLK is 40 MHz, the serial rate is 40 X 12 = 480 Mbps. Since only 10 bits are from input data, the serial

'payload' rate is 10 times the TCLK frequency. For instance, if TCLK = 40 MHz, the payload data is 40 X 10 =

400 Mbps. TCLK is provided by the data source and must be in the range of 16MHz to 66MHz.

When one of six Deserializer channels synchronizes to the input from a Serializer, it drives its LOCKn pin low

and synchronously delivers valid data at its outputs. The Deserializer locks to the embedded clock, uses it to

generate multiple internal data strobes, and drives the embedded clock to the RCLKn pin. The RCLKn pin is

synchronous to the data on the ROUTn[0:9] pins. While LOCKn is low, data on ROUTn[0:9] is valid. Otherwise,

ROUTn[0:9] and RCLKn are high.

All ROUT, LOCK, and RCLK signals will drive a minimum of three CMOS input gates (15pF load) with a 66 MHz

clock. This amount of drive allows bussing outputs of two Deserializers and a destination ASIC. REN controls tri-

state of all the outputs.

The Deserializer input pins are high impedance during Powerdown (PWRDNn or MS_PWRDN low) and power-

Resynchronization

Whenever one of the six Deserializers loses lock, it will automatically try to resynchronize. For example, if the

embedded clock edge is not detected two times in succession, the PLL loses lock and the LOCKn pin is driven

high. The system must monitor the LOCKn pin to determine when data is valid.

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