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SN75183DE4 Datasheet(PDF) 5 Page - Texas Instruments |
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SN75183DE4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 19 page DS8830, SN55183, SN75183 DUAL DIFFERENTIAL LINE DRIVERS SLLS093D – OCTOBER 1972 – REVISED APRIL 1998 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of VCC and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High level output voltage Y (AND) outputs VIH =2V IOH = –0.8 mA 2.4 V VOH High-level output voltage Y (AND) outputs VIH = 2 V IOH = –40 mA 1.8 3.3 V VOL Low level output voltage Y (AND) outputs VIL =0 8V IOL = 32 mA 0.2 V VOL Low-level output voltage Y (AND) outputs VIL = 0.8 V IOL = 40 mA 0.22 0.4 V VOH High level output voltage Z (NAND) outputs VIL =0 8V IOH = –0.8 mA 2.4 V VOH High-level output voltage Z (NAND) outputs VIL = 0.8 V IOH = –40 mA 1.8 3.3 V VOL Low level output voltage Z (NAND) outputs VIH =2V IOL = 32 mA 0.2 V VOL Low-level output voltage Z (NAND) outputs VIH = 2 V IOL = 40 mA 0.22 0.4 V IIH High-level input current VIH = 2.4 V 120 µA II Input current at maximum input voltage VIH = 5.5 V 2 mA IIL Low-level input current VIL = 0.4 V –4.8 mA IOS Short-circuit output current‡ VCC = 5 V, TA =125°C§ –40 –100 –120 mA ICC Supply current (average per driver) VCC = 5 V, All inputs at 5 V, No load 10 18 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted to ground at a time, and duration of the short circuit should not exceed one second. § TA = 125°C is applicable to SN55183 only. switching characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low- to high-level Y output AND gates CL = 15 pF, See FIgure 1(a) 8 12 ns tPHL Propagation delay time, high- to low-level Y output AND gates CL = 15 pF, See FIgure 1(a) 12 18 ns tPLH Propagation delay time, low- to high-level Z output NAND gates CL = 15 pF, See FIgure 1(a) 6 12 ns tPHL Propagation delay time, high- to low-level Z output NAND gates CL = 15 pF, See FIgure 1(a) 6 8 ns tPLH Propagation delay time, low- to high-level differential output Y output with respect to Z output, RL = 100 Ω in series with 5000 pF, See Figure 1(b) 9 16 ns tPHL Propagation delay time, high- to low-level differential output Y output with respect to Z output, RL = 100 Ω in series with 5000 pF, See Figure 1(b) 8 16 ns |
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