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ADUC848BS32-5 Datasheet(PDF) 9 Page - Analog Devices |
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ADUC848BS32-5 Datasheet(HTML) 9 Page - Analog Devices |
9 / 108 page ADuC845/ADuC847/ADuC848 Rev. A | Page 9 of 108 Parameter Min Typ Max Unit Conditions PWM −Fxtal 3 µA −Fvco 0.5 mA TIC 1 µA 3 V Power Consumption 2.7 V < DVDD < 3.6 V, AVDD = 3.6 V Normal Mode11, 12 DVDD Current 4.8 mA Core clock = 1.57 MHz 9 11 mA Core clock = 6.29 MHz (CD = 1) AVDD Current 180 µA ADC not enabled Power-Down Mode11, 12 DVDD Current 20 26 µA TMAX = 85°C; OSC on; TIC on 29 µA TMAX = 125°C; OSC on; TIC on 14 20 µA Tmax = 85°C; OSC off 21 µA TMAX = 125°C; OSC off AVDD Current 1 µA TMAX = 85°C; OSC on or off 3 µA TMAX = 125°C; OSC on or off 1 Temperature range is for ADuC845BS; for the ADuC847BS and ADuC848BS (MQFP package), the range is –40°C to +125°C. Temperature range for ADuC845BCP, ADuC847BCP, and ADuC848BCP (CSP package) is –40°C to +85°C. 2 These numbers are not production tested but are guaranteed by design and/or characterization data on production release. 3 System zero-scale calibration can remove this error. 4 Gain error drift is a span drift. To calculate full-scale error drift, add the offset error drift to the gain error drift times the full-scale input. 5 In general terms, the bipolar input voltage range to the primary ADC is given by the ADC range = ±(VREF 2RN )/1.25, where: VREF = REFIN(+) to REFIN(–) voltage and VREF = 1.25 V when internal ADC VREF is selected. RN = decimal equivalent of RN2, RN1, RN0. For example, if VREF = 2.5 V and RN2, RN1, RN0 = 1, 1, 0, respectively, then the ADC range = ±1.28 V. In unipolar mode, the effective range is 0 V to 1.28 V in this example. 6 1.25 V is used as the reference voltage to the ADC when internal VREF is selected via XREF0/XREF1 or AXREF bits in ADC0CON2 and ADC1CON, respectively. (AXREF is available only on the ADuC845.) 7 In bipolar mode, the auxiliary ADC can be driven only to a minimum of AGND – 30 mV as indicated by the auxiliary ADC absolute AIN voltage limits. The bipolar range is still –VREF to +VREF. 8 DAC linearity and ac specifications are calculated using a reduced code range of 48 to 4095, 0 V to VREF, reduced code range of 100 to 3950, 0 V to VDD. 9 Endurance is qualified to 100 kcycle per JEDEC Std. 22 method A117 and measured at –40°C, +25°C, +85°C, and +125°C. Typical endurance at 25°C is 700 kcycles. 10 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates with junction temperature. 11 Power supply current consumption is measured in normal mode following the power-on sequence, and in power-down modes under the following conditions: Normal mode: reset = 0.4 V, digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, core executing internal software loop. Power-down mode: reset = 0.4 V, all P0 pins and P1.2 to P1.7 pins = 0.4 V. All other digital I/O pins are open circuit, core Clk changed via CD bits in PLLCON, PCON.1 = 1, core execution suspended in power-down mode, OSC turned on or off via OSC_PD bit (PLLCON.7) in PLLCON SFR. 12 DVDD power supply current increases typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle. General Notes about Specifications • DAC gain error is a measure of the span error of the DAC. • The ADuC845BCP, ADuC847BCP, and ADuC848BCP (CSP package) have been qualified and tested with the base of the CSP package floating. The base of the CSP package should be soldered to the board, but left floating electrically, to ensure good mechanical stability. • Flash/EE memory reliability characteristics apply to both the Flash/EE program memory and Flash/EE data memory. |
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