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ADV7300AKST Datasheet(PDF) 10 Page - Analog Devices |
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ADV7300AKST Datasheet(HTML) 10 Page - Analog Devices |
10 / 68 page REV. A –10– ADV7300A/ADV7301A S9–S0 Cb0 Y0 Cr0 Y1 Cb1 Y2 S_HSYNC, S_VSYNC, S_BLANK CONTROL I/PS CLKIN_A t9 t10 t11 t12 SD INPUT t9 t11 CLKIN_B Y9–Y0 t10 t12 t11 t12 CONTROL I/PS P_HSYNC, P_VSYNC, P_BLANK PS INPUT Crxxx Yxxx Cb0 Y0 Cr0 Y1 Figure 10. SD and HD Simultaneous Input, Input Mode: SD and PS 10-Bit (Input Mode at Subaddress 01h = 100) P_HSYNC P_VSYNC P_BLANK Y9–Y0 Cb Y Cr Y b a a = 32 CLKCYCLES FOR 525p a = 24 CLKCYCLES FOR 625p AS RECOMMENDED BY STANDARD b(MIN) = 244 CLKCYCLES FOR 525p b(MIN) = 264 CLKCYCLES FOR 625p Figure 11. PS 4:2:2 1 10-Bit Interleaved @ 54 MHz Input Timing Diagram |
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