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ADV7125KST140 Datasheet(PDF) 11 Page - Analog Devices |
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ADV7125KST140 Datasheet(HTML) 11 Page - Analog Devices |
11 / 12 page REV. 0 ADV7125 –11– channel is used and IOR is terminated with a doubly terminated 75 Ω load (37.5 Ω), IOB and IOG should be terminated with 37.5 Ω resistors (See Figure 5). GND ADV7125 R0 R7 G0 G7 B0 B7 VIDEO INPUT DOUBLY TERMINATED 75 LOAD IOR IOG IOB 37.5 37.5 Figure 5. Input and Output Connections for Standalone Grayscale or Composite Video Video Output Buffers The ADV7125 is specified to drive transmission line loads, as are most monitors rated. The analog output configurations to drive such loads are described in the Analog Outputs section and are illustrated in Figure 6. However, in some applications, it may be required to drive long transmission line cable lengths. Cable lengths greater than 10 meters can attenuate and distort high frequency analog output pulses. The inclusion of output buffers will compensate for some cable distortion. Buffers with large full power bandwidths and gains between two and four will be required. These buffers will also need to be able to supply sufficient current over the complete output voltage swing. Analog Devices produces a range of suitable op amps for such applica- tions. These include the AD84x series of monolithic op amps. In very high frequency applications (80 MHz), the AD8061 is recommended. More information on line driver buffering circuits is given in the relevant op amp data sheets. Use of buffer amplifiers also allows implementation of other video standards besides RS-343A and RS-170. Altering the gain com- ponents of the buffer circuit will result in any desired video level. AD848 0.1 F IOR, IOG, IOB Z1 Z2 ZO = 75 (CABLE) ZS = 75 (SOURCE TERMINATION) ZL = 75 (MONITOR) DACs 75 –VS +VS 0.1 F GAIN (G) = 1 + Z1 Z2 Figure 6. AD848 As an Output Buffer PC Board Layout Considerations The ADV7125 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the excel- lent noise performance of the ADV7125, it is imperative that great care be given to the PC board layout. Figure 7 shows a recommended connection diagram for the ADV7125. The layout should be optimized for lowest noise on the ADV7125 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins should by minimized to minimize inductive ringing. Ground Planes The ADV7125 and associated analog circuitry should have a separate ground plane referred to as the analog ground plane. This ground plane should connect to the regular PCB ground plane at a single point through a ferrite bead, as illustrated in Figure 7. This bead should be located as close as possible (within three inches) to the ADV7125. The analog ground plane should encompass all ADV7125 ground pins, voltage reference circuitry, power supply bypass circuitry, the analog output traces, and any output amplifiers. The regular PCB ground plane area should encompass all the digital signal traces, excluding the ground pins, leading up to the ADV7125. Power Planes The PC board layout should have two distinct power planes, one for analog circuitry and one for digital circuitry. The analog power plane should encompass the ADV7125 (VAA) and all associated analog circuitry. This power plane should be con- nected to the regular PCB power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 6. This bead should be located within three inches of the ADV7125. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7125 power pins, voltage reference circuitry, and any output amplifiers. The PCB power and ground planes should not overlay portions of the analog power plane. Keeping the PCB power and ground planes from overlaying the analog power plane will contribute to a reduction in plane-to-plane noise coupling. Supply Decoupling Noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors (see Figure 7). Optimum performance is achieved by the use of 0.1 µF ceramic capacitors. Each of the two groups of VAA should be individually decoupled to ground. This should be done by placing the capaci- tors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. It is important to note that while the ADV7125 contains circuitry to reject power supply noise, this rejection decreases with fre- quency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise. A dc power supply filter (Murata BNX002) will provide EMI suppression between the switching power supply and the main PCB. Alternatively, consideration could be given to using a three-terminal voltage regulator. Digital Signal Interconnect The digital signal lines to the ADV7125 should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. Due to the high clock rates used, long clock lines to the ADV7125 should be avoided to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC) and not the analog power plane. |
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