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ADV7300A Datasheet(PDF) 62 Page - Analog Devices |
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ADV7300A Datasheet(HTML) 62 Page - Analog Devices |
62 / 68 page REV. A –62– ADV7300A/ADV7301A Mode 2: Slave Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 0) In this mode, the ADV7300A/ADV7301A accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7300A/ADV7301A auto- matically blanks all normally blank lines as per CCIR-624. HSYNC is input on the S_HSYNC pin, BLANK on the S_BLANK pin, and FIELD on the S_VSYNC pin. 522 523 524 525 1234 5 678 9 10 11 20 21 22 DISPLAY DISPLAY VERTICAL BLANK ODD FIELD EVEN FIELD 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 ODD FIELD EVEN FIELD DISPLAY DISPLAY VERTICAL BLANK HSYNC BLANK VSYNC HSYNC BLANK VSYNC Figure 101. SD Slave Mode 2, NTSC 622 623 624 625 1234 5 67 21 22 23 DISPLAY VERTICAL BLANK ODD FIELD EVEN FIELD HSYNC BLANK VSYNC DISPLAY 309 310 311 312 313 314 315 316 317 318 319 334 335 336 DISPLAY VERTICAL BLANK ODD FIELD EVEN FIELD DISPLAY 320 HSYNC BLANK VSYNC Figure 102. SD Slave Mode 2, PAL |
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