LM10692BRMYR datasheet(39/48 Pages) TI1

Part #	LM10692BRMYR

Description	LM10692 Power Management Unit for SandForce SF3700 SSD Controllers

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Manufacturer	TI1 [Texas Instruments]

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LM10692

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SNVSA53 – JULY 2014

11 Layout

11.1 Layout Guidelines

Proper layout of the PCB is critical to the proper operation of the IC. A compact layout will yield better

performances as well as an overall reduced footprint for the solution.

Of prime importance is the location of the input capacitors. Those need to be close to the IC’s power input they

are assigned to in order to reduce the parasitic inductance between the input and the power rails inside the IC.

The output capacitors should be connected close to the GND of the input capacitors of the same channel. This is

because current flows from the input capacitor (through the inductor) to the output capacitor and the load during

the part of the switching cycle when the HS FET is ON.

Inductors should be close to the switch nodes. The path from the switch node pin and the inductor pad should be

minimized. It is a good practice to keep the PCB from having any copper such as ground planes underneath the

inductor pad on the switch node side to reduce switch node capacitance. Increased switch node capacitance can

lead to lower efficiency as it increases the turn-on and turn-off time of the FET and thereby increases switching

losses.

Signal traces should avoid crossing underneath the switch node traces and pads or passing between the

inductor’s pads in order to avoid noise from the switch node and the magnetic components to couple into these

lines. This applies particularly to the feedback lines.

To increase thermal conductivity and help carry heat away from the IC, the planes should have as large surfaces

as possible, which is applicable in particular to PVIN and GND with regard to the IC. This also applies to the six

outputs lines in order to spread the heat generated on each of the inductors.

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