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LDC1000NHRR Datasheet(PDF) 7 Page - Texas Instruments |
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LDC1000NHRR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 36 page tODZ ttCSSt SCLK SDO CSB tCSH 1 st Clock 8 th Clock 16 th Clock D7 D1 D0 tOD tOZD ttIAGt ttCSHt ttHt ttPLt ttPHt tSU Valid Data Valid Data SCLK SDI LDC1000 www.ti.com SNOSCX2C – SEPTEMBER 2013 – REVISED SEPTEMBER 2015 6.6 Timing Requirements Unless otherwise noted, all limits specified at TA = 25°C, VDD=5.0, VIO=3.3, 10 pF capacitive load in parallel with a 10 k Ω load on SDO. Specified by design; not production tested. MIN NOM MAX UNIT ƒSCLK Serial Clock Frequency 4 MHz tPH SCLK Pulse Width High ƒSCLK = 4 MHz 0.4 / ƒSCLK s tPL SCLK Pulse Width Low ƒSCLK = 4 MHz 0.4 / ƒSCLK s tSU SDI Setup Time 10 ns tH SDI Hold Time 10 ns tODZ SDO Driven-to-Tristate Time Measured at 10% / 90% point 20 ns tOZD SDO Tristate-to-Driven Time Measured at 10% / 90% point 20 ns tOD SDO Output Delay Time 20 ns tCSS CSB Setup Time 20 ns tCSH CSB Hold Time 20 ns tIAG Inter-Access Gap 100 ns tDRDYB Data ready pulse width Data ready pulse at every 1 / ODR if no 1 / ƒsensor s data is read Figure 1. Write Timing Diagram Figure 2. Read Timing Diagram Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LDC1000 |
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