SCLK

SDO

CSB

1

8

16

D7

D1

D0

Valid Data

Valid Data

SCLK

SDI

LDC1000

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SNOSCX2C – SEPTEMBER 2013 – REVISED SEPTEMBER 2015

6.6 Timing Requirements

Unless otherwise noted, all limits specified at TA = 25°C, VDD=5.0, VIO=3.3, 10 pF capacitive load in parallel with a 10 k

Ω

load on SDO. Specified by design; not production tested.

MIN

NOM

MAX

UNIT

Serial Clock Frequency

4

MHz

SCLK Pulse Width High

s

SCLK Pulse Width Low

s

SDI Setup Time

10

ns

SDI Hold Time

10

ns

SDO Driven-to-Tristate Time

Measured at 10% / 90% point

20

ns

SDO Tristate-to-Driven Time

Measured at 10% / 90% point

20

ns

SDO Output Delay Time

20

ns

CSB Setup Time

20

ns

CSB Hold Time

20

ns

Inter-Access Gap

100

ns

Data ready pulse width

Data ready pulse at every 1 / ODR if no

s

data is read

Figure 1. Write Timing Diagram

Figure 2. Read Timing Diagram

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