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ADSP-BF533SBBZ500 Datasheet(PDF) 16 Page - Analog Devices |
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ADSP-BF533SBBZ500 Datasheet(HTML) 16 Page - Analog Devices |
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16 / 56 page  Rev. 0 | Page 16 of 56 | March 2004 ADSP-BF531/ADSP-BF532/ADSP-BF533 PIN DESCRIPTIONS ADSP-BF531/2/3 processor pin definitions are listed in Table 9. All pins are three-stated during and immediately after reset, except the Memory Interface, Asynchronous Memory Control, and Synchronous Memory Control pins, which are driven high. If BR is active, then the memory pins are also three-stated. All unused I/O pins have their input buffers disabled with the exception of the pins that need pullups or pulldowns as noted in the table footnotes. In order to maintain maximum functionality and reduce pack- age size and pin count, some pins have dual, multiplexed functionality. In cases where pin functionality is reconfigurable, the default state is shown in plain text, while alternate function- ality is shown in italics. Table 9. Pin Descriptions Pin Name I/O Function Driver Type1 Memory Interface ADDR19–1 O Address Bus for Async/Sync Access A2 DATA15–0 I/O Data Bus for Async/Sync Access A2 ABE1–0/SDQM1–0 O Byte Enables/Data Masks for Async/Sync Access A2 BR3 IBus Request BG OBus Grant A2 BGH OBus Grant Hang A2 Asynchronous Memory Control AMS3–0 OBank Select A2 ARDY I Hardware Ready Control AOE OOutput Enable A2 ARE ORead Enable A2 AWE OWrite Enable A2 Synchronous Memory Control SRAS O Row Address Strobe A2 SCAS O Column Address Strobe A2 SWE OWrite Enable A2 SCKE O Clock Enable A2 CLKOUT O Clock Output B4 SA10 O A10 Pin A2 SMS OBank Select A2 Timers TMR0 I/O Timer 0 C5 TMR1/PPI_FS1 I/O Timer 1/PPI Frame Sync1 C5 TMR2/PPI_FS2 I/O Timer 2/PPI Frame Sync2 C5 |
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