DS99R105, DS99R106

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SNLS242D – MARCH 2007 – REVISED APRIL 2013

Electrical Characteristics

(1)(2)(3) (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Parameter

Test Conditions

Pin/Freq.

Min

Typ

Max

Units

SER/DES SUPPLY CURRENT (DVDD*, PVDD* and AVDD* pins) *Digital, PLL, and Analog VDDs

Serializer (Tx)

f = 40 MHz

Total Supply Current

Pre-emphasis = OFF

40

80

mA

(includes load current)

VODSEL = L

Checker-board pattern (Figure 2)

f = 40 MHz

Pre-emphasis = ON

45

85

mA

VODSEL = L

Checker-board pattern (Figure 2)

Serializer (Tx)

f = 40 MHz

Total Supply Current

Pre-emphasis = OFF

40

85

mA

(includes load current)

VODSEL = H

Checker-board pattern (Figure 2)

f = 40 MHz

Pre-emphasis = ON

45

90

mA

VODSEL = H

Checker-board pattern (Figure 2)

Serializer (Tx)

TPWDNB = 0V

1

100

µA

Supply Current Power-down

(All other LVCMOS Inputs = 0V)

Deserializer (Rx)

f = 40 MHz

Total Supply Current

Checker-board pattern

95

mA

(includes load current)

(Figure 3)

Deserializer (Rx)

f = 40 MHz

Total Supply Current

Random pattern

90

mA

(includes load current)

Deserializer (Rx)

RPWDNB = 0V

Supply Current Power-down

(All other LVCMOS Inputs = 0V,

1

50

µA

Serializer Timing Requirements for TCLK

(1) (2)

Over recommended operating supply and temperature ranges unless otherwise specified.

Parameter

Test Conditions

Min

Typ

Max

Units

Transmit Clock Period

(Figure 6)

25

T

333

ns

Transmit Clock High Time

0.4T

0.5T

0.6T

ns

Transmit Clock Low Time

0.4T

0.5T

0.6T

ns

TCLK Input Transition Time

(Figure 5)

3

6

ns

TCLK Input Jitter

(3)

33

ps (RMS)

(1)

Figure 2, Figure 3, Figure 9, Figure 13, and Figure 15 show a falling edge data strobe (TCLK IN/RCLK OUT).

(2)

Figure 6 and Figure 16 show a rising edge data strobe (TCLK IN/RCLK OUT).

(3)

Serializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Parameter

Test Conditions

Min

Typ

Max

Units

LVDS Low-to-High Transition Time

0.6

ns

LVDS High-to-Low Transition Time

0.6

ns

VODSEL = L

DIN (23:0) Setup to TCLK

5

ns

DIN (23:0) Hold from TCLK

5

ns

(1)

(1)

Specification is ensured by characterization and is not tested in production.

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