DS99R105, DS99R106

SNLS242D – MARCH 2007 – REVISED APRIL 2013

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Serializer Switching Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Parameter

Test Conditions

Min

Typ

Max

Units

DOUT ± HIGH to TRI-STATE Delay

15

ns

DOUT ± LOW to TRI-STATE Delay

15

ns

(Figure 7)(2)

DOUT ± TRI-STATE to HIGH Delay

200

ns

DOUT ± TRI-STATE to LOW Delay

200

ns

Serializer PLL Lock Time

10

ms

Serializer Delay

3.5T +

3.5T +

ns

VODSEL = L, TRFB = H

2.85

10

3.5T +

3.5T +

ns

VODSEL = L, TRFB = L

2.85

10

TxOUT_E_O

TxOUT_Eye_Opening

3–40 MHz

UI

0.68

(respect to ideal)

(Figure 10)(3) (4)

(5)

(2)

When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.

(3)

(4)

TxOUT_E_O is affected by pre-emphasis value.

(5)

UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.

Deserializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Parameter

Test Conditions

Pin/Freq.

Min

Typ

Max

Units

Receiver out Clock Period

(1)

RCLK

25

T

333

ns

RCLK Duty Cycle

RCLK

45

50

55

%

LVCMOS Low-to-High

ROUT [23:0],

2.5

3.5

ns

Transition Time

(lumped load)

LOCK, RCLK

(Figure 12)

LVCMOS High-to-Low

2.5

3.5

ns

Transition Time

ROUT (7:0) Setup Data to RCLK

(Figure 16)

ROUT [7:0]

(0.40)*

ns

(Group 1)

ROUT (7:0) Hold Data to RCLK

(0.40)*

ns

(Group 1)

ROUT (15:8) Setup Data to RCLK

(Figure 16)

ROUT [15:8],

(0.40)*

ns

(Group 2)

LOCK

ROUT (15:8) Hold Data to RCLK

(0.40)*

ns

(Group 2)

ROUT (23:16) Setup Data to

(Figure 16)

ROUT [23:16]

(0.40)*

ns

RCLK (Group 3)

ROUT (23:16) Hold Data to RCLK

(0.40)*

ns

(Group 3)

HIGH to TRI-STATE Delay

(Figure 14)

ROUT [23:0],

3

10

ns

RCLK, LOCK

LOW to TRI-STATE Delay

3

10

ns

TRI-STATE to HIGH Delay

3

10

ns

TRI-STATE to LOW Delay

3

10

ns

Deserializer Delay

(Figure 13)

RCLK

[4+(3/56)]T

[4+(3/56)]T

ns

+5.9

+18.5

Deserializer PLL Lock Time from

(Figure 15)

3 MHz

5

50

ms

Powerdown

(2) (1)

40 MHz

5

50

ms

RxIN_TOL_L

Receiver INput TOLerance Left

3 MHz–40 MHz

0.25

UI

RxIN_TOL_R Receiver INput TOLerance Right

3 MHz–40 MHz

0.25

UI

(1)

Specification is ensured by characterization and is not tested in production.

(2)

(3)

RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors

occur. It is a measurement in reference with the ideal bit position, please see TI’s AN-1217 (SNLA053) for detail.

(4)

UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.

6

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