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DS99R124Q-Q1 Datasheet(PDF) 8 Page - Texas Instruments |
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DS99R124Q-Q1 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 31 page  DS99R124Q SNLS318D – JANUARY 2010 – REVISED APRIL 2013 www.ti.com Switching Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. (1)(2) Symbol Parameter Conditions Pin/Freq. Min Typ Max Units tTLHT Low to High Transition Time RL = 100Ω TxCLKOUT±, 0.3 0.6 ns TxOUT[2:0]± tTHLT High to Low Transition Time 0.3 0.6 ns tDCCJ Cycle-to-Cycle Output Jitter(4)(5) TxCLKOUT = 5 MHz TxCLKOUT± 900 2100 ps TxCLKOUT = 43 MHz 75 125 ps tTTP1 Transmitter Pulse Position for TxOUT[2:0]± 0 UI bit 1 tTTP0 Transmitter Pulse Position for 1 UI bit 0 tTPP6 Transmitter Pulse Position for 2 UI bit 6 tTTP5 Transmitter Pulse Position for 3 UI bit 5 tTTP4 Transmitter Pulse Position for 4 UI bit 4 tTTP3 Transmitter Pulse Position for 5 UI bit 3 tTTP2 Transmitter Pulse Position for 6 UI bit 2 tTPDD Power Down Delay active to TxCLKOUT = 43 MHz OFF 6 10 ns Figure 6 tTXZR Enable Delay OFF to active TxCLKOUT = 43 MHz 40 55 ns Figure 7 LVCMOS Outputs tCLH Low to High Transition Time CL = 8 pF LOCK, PASS, OS[2:0] 10 15 ns Figure 5 tCHL High to Low Transition Time 10 15 ns tPASS BIST PASS Valid Time, TxCLKOUT = 5 MHz PASS 560 570 ns BISTEN = 1, Figure 12 TxCLKOUT = 43 MHz 70 75 ns SSCG Mode fDEV Spread Spectrum See(6) TxCLKOUT = 5 to 43 Clocking Deviation MHz, ±0.5 ±2 % Frequency SSC[3:0] = ON fMOD Spread Spectrum See(6) TxCLKOUT = 5 to 43 Clocking Modulation MHz, 8 100 kHz Frequency SSC[3:0] = ON (4) tDCCJ is the maximum amount of jitter between adjacent clock cycles. (5) Specification is ensured by characterization and is not tested in production. (6) Specification is ensured by design and is not tested in production. Recommended Timing for the Serial Control Bus Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units fSCL SCL Clock Frequency Standard Mode 0 100 kHz Fast Mode 0 400 kHz tLOW SCL Low Period Standard Mode 4.7 us Fast Mode 1.3 us tHIGH SCL High Period Standard Mode 4.0 us Fast Mode 0.6 us tHD;STA Hold time for a start or a Standard Mode 4.0 us repeated start condition, Fast Mode 0.6 us Figure 13 8 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS99R124Q |
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