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DS96F175C Datasheet(PDF) 7 Page - Texas Instruments |
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DS96F175C Datasheet(HTML) 7 Page - Texas Instruments |
7 / 12 page DS96F173M/DS96F175C/DS96F175M www.ti.com SNOSC40F – JULY 2000 – REVISED APRIL 2013 MIL-STD-883C Switching Characteristics VCC = 5.0V Symbol Parameter Conditions TA = 25°C TA = −55°C TA = 125°C Units Typ Max Max Max tPLH Propagation Delay Time, Low to VID = −2.5V to +2.5V, 15 22 30 30 ns High Level Output CL = 15 pF, See Figure 7 tPHL Propagation Delay Time, High to VCM = 0V 15 22 30 30 ns Low Level Output tZH Output Enable Time to High Level CL = 15 pF, See Figure 8 12 16 27 27 ns tZL Output Enable Time to Low Level CL = 15 pF, See Figure 9 13 18 27 27 ns tHZ Output Disable Time from High CL = 5.0 pF, See Figure 8 (1) 14 20 27 27 ns Level CL = 20 pF, See Figure 8 (1) 14 30 37 37 ns tLZ Output Disable Time from Low CL = 5.0 pF, See Figure 9 14 18 30 30 ns Level |tPLH–tPHL| Pulse Width Distortion (SKEW) See Figure 7 1 3 5.0 5.0 ns (1) Testing at 20 pF assures conformance to 5 pF specification. Connection Diagrams Figure 2. DS96F175 (Top View)(2) 16-Lead Ceramic Dual-In-Line CDIP Package Figure 1. DS96F173 (Top View)(2) Package Number NFE 16-Lead Ceramic Dual-In-Line CDIP Package Package Number NFE (2) DS96F173 with active high and active low Enables are shown. DS96F175 has active high Enable only. Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DS96F173M/DS96F175C/DS96F175M |
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