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DP83916 Datasheet(PDF) 67 Page - National Semiconductor (TI) |
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DP83916 Datasheet(HTML) 67 Page - National Semiconductor (TI) |
67 / 96 page 50 Bus Interface (Continued) 548 On-Chip Memory Arbiter For applications which share the buffer memory area with the host system (shared-memory applications) the SONIC- 16 provides a fast on-chip memory arbiter for efficiently re- solving accesses between the SONIC-16 and the host sys- tem ( Figure 5-25 ) The host system indicates its intentions to use the shared-memory by asserting Memory Request (MREQ) The SONIC-16 will allow the host system to use the shared memory by acknowledging the host system’s re- quest with Slave and Memory Acknowledge (SMACK) Once SMACK is asserted the host system may use the shared memory freely The host system gives up the shared memory by deasserting MREQ MREQ is clocked in on the falling edge of bus clock and is double synchronized internally to the rising edge SMACK is asserted on the falling edge of a Ts bus cycle If the SONIC- 16 is not currently accessing the memory SMACK is assert- ed immediately after MREQ was clocked in If however the SONIC-16 is accessing the shared memory it finishes its current memory transfer and then issues SMACK SMACK will be asserted 1 or 5 (see Note 2 below) bus clocks re- spectively after MREQ is clocked in Since MREQ is double synchronized it is not necessary to meet its setup time Meeting the setup time for MREQ will however guarantee that SMACK is asserted in the next or fifth bus clock after the current bus clock SMACK will deassert within one bus clock after MREQ is deasserted The SONIC-16 will then finish its master operation if it was using the bus previously If the host system needs to access the SONIC-16’s regis- ters instead of shared memory CS would be asserted in- stead of MREQ Accessing the SONIC-16’s registers works almost exactly the same as accessing the shared memory except that the SONIC-16 goes into a slave cycle instead of going idle See Section 547 for more information about how register accesses work Note 1 The successive assertion of CS and MREQ must be separated by at least two bus clocks Both CS and MREQ must not be asserted concurrently Note 2 The number of bus clocks between MREQ being asserted and the assertion of SMACK when the SONIC-16 is in Master Mode is 5 bus clocks assuming there were no wait states in the Master Mode access Wait states will increase the time for SMACK to go low by the number of wait states in the cycle (the time will be 5 a the number of wait states) Note 3 The way in which SMACK is asserted to due to CS is not the same as the way in which SMACK is asserted due to MREQ SMACK goes low as a direct result of the assertion of MREQ whereas for CS SAS must also be driven low (BMODE e 1) or high (BMODE e 0) before SMACK will be asserted This means that when SMACK is asserted due to MREQ SMACK will remain asserted until MREQ is deasserted Multiple memory accesses can be made to the shared memory without SMACK ever going high When SMACK is asserted due to CS however SMACK will only remain low as long as SAS is also low (BMODE e 1) or high (BMODE e 0) SMACK will not remain low throughout multiple register accesses to the SONIC-16 because SAS must toggle for each register access This is an important difference to consider when designing shared mem- ory designs TABLE 5-4 Internal Register Content after Reset Register Contents after Reset Hardware Software Reset Reset Command 0094h 0094h00A4h Data Configuration unchanged (DCR and DCR2) Interrupt Mask 0000h unchanged Interrupt Status 0000h unchanged Transmit Control 0101h unchanged Receive Control unchanged End Of Buffer Count 02F8h unchanged Sequence Counters 0000h unchanged CAM Enable 0000h unchanged Bits 15 and 13 of the DCR and bits 4 through 0 of the DCR2 are reset to a 0 during a hardware reset Bits 15-12 of the DCR2 are unknown until written to All other bits in these two registers are unchanged Bits LB1 LB0 and BRD are reset to a 0 during hardware reset All other bits are unchanged 549 Chip Reset The SONIC-16 has two reset modes a hardware reset and a software reset The SONIC-16 can be hardware reset by asserting the RESET pin or software reset by setting the RST bit in the Command Register (Section 431) The two reset modes are not interchangeable since each mode per- forms a different function After power-on the SONIC-16 must be hardware reset be- fore it will become operational This is done by asserting RESET for a minimum of 10 transmit clocks (10 Ethernet transmit clock periods TXC) If the bus clock (BSCK) period is greater than the transmit clock period RESET should be asserted for 10 bus clocks instead of 10 transmit clocks A hardware reset places the SONIC-16 in the following state (The registers affected are listed in parentheses See Table 5-4 and section 43 for more specific information about the registers and how they are affected by a hardware reset Only those registers listed below and in Table 5-4 are affect- ed by a hardware reset) 1 Receiver and Transmitter are disabled (CR) 2 The General Purpose timer is halted (CR) 3 All interrupts are masked out (IMR) 4 The NCRS and PTX status bits in the Transmit Control Register (TCR) are set 5 The End Of Byte Count (EOBC) register is set to 02F8h (760 words) 6 Packet and buffer sequence number counters are set to zero 7 All CAM entries are disabled The broadcast address is also disabled (CAM Enable Register and the RCR) 8 Loopback operation is disabled (RCR) 9 The latched bus retry is set to the unlatched mode (DCR) 10 All interrupt status bits are reset (ISR) 11 The Extended Bus Mode is disabled (DCR) 12 HOLD will be asserteddeasserted from the falling clock edge (DCR2) 67 |
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